EE 143 Microfabrication Technology Lecture 21m Interconnects Contacts CTN Sintering 4 8 10 Al Spiking Junction Penetration Problem taking the temperature up too high causes silicon Usually need a forming gas anneal 400 450oC called to diffuse into Al Supply of Si tends to come from a few points that then leave caves that Al can then go into to form spikes This happens because the silicon wants to diffuse into the Al till it reaches its solid solubility limit of 0 25 1 5 sintering at the end of an NMOS or CMOS process Forming gas mixture of H2 and N2 Improves the metal to silicon contact Reduces the oxide interface charge allowing the threshold voltage to be the right value The H2 ties up dangling bonds that would otherwise contribute fixed interface charge To prevent this can Incorporate Si into the Al so that it s closer to its solid solubility limit usually add 1 Si to the Al target in sputtering Use a barrier metal e g TiW Use a barrier silicide If you finish an MOS process and your thresholds are off don t despair just do a sintering step this will probably fix your problems almost like magic EE 143 Microfabrication Technology LecM 7 C Nguyen 3 14 10 8 Contact Resistance LecM 7 C Nguyen 3 14 10 9 Measuring Contact Resistance Your lab layout includes contact chains Definition Resistance EE 143 Microfabrication Technology associated with the contact between two materials Inversely proportional to the area of the contact Metal Diffusion Contacts Metal PolySi Contacts Rc c A Each chain 14 series contacts and 7 series resistive pads Strategy if one uses enough contacts the contact Strong function of the sintering temperature EE 143 Microfabrication Technology resistance becomes large enough to measure Problem segment resistance also rises how can one LecM 7 C Nguyen 3 14 10 10 delineate the contact resistance EE 143 Microfabrication Technology Copyright 2010 Regents of the University of California at Berkeley LecM 7 C Nguyen 3 14 10 11 EE 143 Microfabrication Technology Lecture 21m Interconnects Contacts CTN Measuring Contact Resistance Electromigration Solution use a 4 pt probe strategy also on the layout Definition The movement of atoms in a metal film due to momentum transfer from the electrons carrying the current Happens under high current density Metal PolySi Contact Resistance Test Structure EE 143 Microfabrication Technology 4 8 10 Mean time to failure MTF formula MTF J LecM 7 C Nguyen 3 14 10 12 Electromigration 2 where J current density EA activation energy 0 4 0 5eV for Al E exp A kT EE 143 Microfabrication Technology LecM 7 C Nguyen 3 14 10 13 Issue Polysilicon to Metal Contact To reduce electromigration can add a small percentage of a Polysilicon to metal contact takes up space Need to eliminate waste of space for the smallest circuits heavier metal like Cu to Al Cu has higher mass more resistant to electromigration Targets composed of 95 Al 4 Cu and 1 Si often used in sputtering systems like memory arrays Below conventional layout Wasted Space EE 143 Microfabrication Technology LecM 7 C Nguyen 3 14 10 14 EE 143 Microfabrication Technology Copyright 2010 Regents of the University of California at Berkeley LecM 7 C Nguyen 3 14 10 15 EE 143 Microfabrication Technology Lecture 21m Interconnects Contacts CTN Buried Contact 4 8 10 Butted Contact Need to add a mask to allow a buried contact but it can Saves area since it only needs one contact to connect save space and make the most compact layout polysilicon and metal Diffusion from the n polySi merges with the S D diffusion around the gate the diffusion cannot be initially below the gate since the gate serves as a mask against the source drain implant EE 143 Microfabrication Technology LecM 7 C Nguyen 3 14 10 16 EE 143 Microfabrication Technology Silicide LecM 7 C Nguyen 3 14 10 17 The Silicidation Process Sheet resistance of polysilicon and shallow diffusions used in CMOS are generally on the order of 10 20 Can reduce this resistance to 15 50 by reacting silicon with a noble or refractory metal to form a silicide Expose silicon areas where silicidation is desired Blanket deposit metal Heat to needed temperature can be done via rapid thermal anneal RTA Remove unreacted metal EE 143 Microfabrication Technology LecM 7 C Nguyen 3 14 10 18 EE 143 Microfabrication Technology Copyright 2010 Regents of the University of California at Berkeley LecM 7 C Nguyen 3 14 10 19 EE 143 Microfabrication Technology Lecture 21m Interconnects Contacts CTN The Silicidation Process Lift Off Remarks 1 Often can be self aligned to the region to be silicided in which case it s called a salicide 2 Polycide a silicide over polysilicon Also pretty much self aligned Just put the metal down everywhere heat and reaction will only occur over polysilicon areas 3 Achieve resistivities from 15 50 cm 4 Can oxidize the surface of a silicide since silicon diffuses through the silicide to combine with the oxidant 5 Unlike silicon metals that are unreacted many silicides can take temperatures much higher than the eutectic temperature over 1000oC not true for all silicides e g nickel silicide 900oC platinum silicide 800oC and palladium silicide 700oC EE 143 Microfabrication Technology LecM 7 C Nguyen 3 14 10 4 8 10 20 Many metals e g Conventional Lift Off nickel copper do not have a recipe for dry etching so cannot be etched anisotropically with good resolution Lift off provides a method for patterning a metal without the need for etching Right comparison of conventional and liftoff based metallization processes EE 143 Microfabrication Technology Multilevel Metallization LecM 7 C Nguyen 3 14 10 21 Damescene Process Big Problem for multi levels of metal topography Employs plating through molds to achieve contact plugs in a Interferes with lithography degrading resolution Creates stringers that then force overetching fully planarized via CMP cross section Solution planarization and contact plugs EE 143 Microfabrication Technology LecM 7 C Nguyen 3 14 10 22 EE 143 Microfabrication Technology Copyright 2010 Regents of the University of California at Berkeley LecM 7 C Nguyen 3 14 10 23 EE 143 Microfabrication Technology Lecture 21m Interconnects Contacts CTN Dual Damescene Process Dual Damescene Process Do multiple steps in one step Form interconnect lines and vias between interconnect levels Do multiple steps in one step Form interconnect lines and vias between interconnect levels all at the same time EE 143 Microfabrication Technology LecM 7 C Nguyen 3 14 10 4 8
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