EE 143 Microfabrication Technology Lecture 21n Advanced CMOS EE 143 CTN CMOS Process Flow CTN D G Sub G S G P S D N 1 D Sub S 4 8 10 S N P N Well PMOS Substrate D G P N P Well NMOS Substrate P Copyright 2010 Regents of the University of California at Berkeley 1 EE 143 Microfabrication Technology Lecture 21n Advanced CMOS EE 143 CTN CMOS Process Flow Photoresist Si3N4 SiO2 CTN 4 8 10 2 Substrate selection moderately high resistivity 100 orientation P type Wafer cleaning thermal oxidation 40 nm nitride LPCVD deposition 80 nm photoresist spinning and baking 0 5 1 0 m Si 100 P Type 5 50 cm Mask 1 patterns the active areas The nitride is dry etched P Field oxide is grown using a LOCOS process Typically 90 min 1000 C in H2O grows 0 5 m P Boron P Implant Mask 2 blocks a B implant to form the wells for the NMOS devices Typically 1013 cm 2 150 200 KeV P Copyright 2010 Regents of the University of California at Berkeley 2 EE 143 Microfabrication Technology Lecture 21n Advanced CMOS EE 143 CTN CMOS Process Flow CTN 4 8 10 3 Phosphorus N Implant P Implant Mask 3 blocks a P implant to form the wells for the PMOS devices Typically 1013 cm 2 300 KeV P N Well P Well P A high temperature drive in produces the final well depths and repairs implant damage Typically 4 6 hours 1000 C 1100 C or equivalent Dt Boron P N Well P Well P Mask 4 is used to mask the PMOS devices A VTH adjust implant is done on the NMOS devices typically a 1 5 x 1012 cm 2 B implant 50 75 KeV Arsenic N P N Well P Well P Copyright 2010 Regents of the University of California at Berkeley Mask 5 is used to mask the NMOS devices A VTH adjust implant is done on the PMOS devices typically 1 5 x 1012 cm 2 As implant 75 100 KeV 3 EE 143 Microfabrication Technology Lecture 21n Advanced CMOS EE 143 CTN CMOS Process Flow N P N Well P Well P N P N Well P Well CTN 4 8 10 4 The thin oxide over the active regions is stripped and a new gate oxide grown typically 3 5 nm which could be grown in 0 5 1 hrs 800 C in O2 Polysilicon is deposited by LPCVD 0 5 m An unmasked P or As implant dopes the poly typically 5 x 1015 cm 2 P N P N Well P Well Mask 6 is used to protect the MOS gates The poly is plasma etched using an anisotropic etch P Phosphorus P N N Implant N Well P Well Mask 7 protects the PMOS devices A P implant forms the LDD regions in the NMOS devices typically 5 x 1013 cm 2 50 KeV P Copyright 2010 Regents of the University of California at Berkeley 4
View Full Document
Unlocking...