EE143 Fall 2005 Homework Assignment 9 Due Nov 17 9 30am together with HW 10 Reading Assignment 1 Jaeger pp 212 221 2 Summary sheet of EE143 layout rules attached 3 EE143 Reader Week 11 Design Rule Basics from Physical Design of CMOS IC Using L Edit J P Uyemura This general reading provides bakground information on why different rules are needed Read here before you start your homework The layout schematics shown below are not to scale The exact layout may depend on the constraints imposed by the design rules You have to do all layouts with a scale of 0 2 to 1 A graph paper with such a scale is attched is also posted on the web You can photocopy it for your homework problems The reader will not grade any homework turned in with other arbitrary scales You have to draw the layout and specify which design rules are used If you wish you can also use color pencils to distinguish the different boundaries Note 1 Active device region is also called Thin oxide region 2 The S D area is also called the diffusion region although it is doped by ion implantation Problem 1 Two contact holes inside the Source and Drain of a MOSFET The following layout of a MOSFET hasa given L 4 and W 8 Use the EE143 layout graph paper to layout a minimum size transistor Label the design rules you used Field Oxide W L L channel length W channel width Note An integrated circuit usually has MOSFETs with different L and W values To reduce the contact resistance it is desirable to maximize the metal contact area to the source drain regions To optimize optical lithography and reactive ion etching steps it is preferable to place several identical size contact holes within the S D regions instead of a single large one 1 Problem 2 NMOS Inverter Layout a minimum geometry NMOS poly gate inverter with the EE143 design rules in the graph paper provided The circuit diagram and the schematic cross section are shown below Vin Vout and VDD are the input voltage line output voltage line and supply voltage line respectively All interconnects are aluminum lines Both transistors have W 4 m 2 and L 4 m 2 The poly gate of transistor T2 is electrically connected to its drain with an aluminum line Dash lines indicate contact cut to the poly Si is to the VDD V in V VDD out T2 SiO2 V n out T1 V in n n p substrate Problem 3 NOR Gate Use our EECS143 design rules to draw a minimum geometry two input NMOS NOR gate using poly Si gate transistors VDD is connected to the gate of T3 with Al line To conserve space and to minimize the number of contact holes the n diffusion regions are merged wherever possible GIVEN T1 and T2 W L 10 m 4 m T3 W L 4 m 10 m To help you started an unfinished not to scale sketch of the top view is provided Any reasonable deviation from this sketch is acceptable Draw the composite layout including metal lines and state the design rule used VDD VDD T3 T3 poly A B A B A T1 n diffusion T2 B A B T1 2 T2 Problem 4 How design rules can be changed The following cross section shows a CMOS inverter fabricated with silicon on sapphire SOS technology Sapphire Al2O3 is a perfect insulator If we choose to use this technology Explain how three of our EECS143 MOS layout design rules can be changed larger or smaller Justify your explanations 3 EE143 Standard Layout symbols and Design Rules 1 Background 1 1 Lithography etching limit on minimum feature or spacing 2 1 2 Alignment limit overlay accuracy 1 3 Unless specified default value 2 m 2 Symbols and Rules 2 2 1 Contacts metal to silicon minimum size 2 x 2 2 2 2 Metal minimum width 2 minimum spacing 3 minimum underlap of contact 2 metal line 3 spacing metal line 2 2 3 Polysilicon minimum width 2 minimum spacing 2 minimum underlap of contact 2 poly line metal line spacing 2 poly line 3 MOS Devices 3 1 Thin oxide of MOS minimum width 2 minimum space 3 minimum underlap of contact 2 Thin Oxide Field Oxide The thin oxide region is also known as diffusion region The field oxide region is also called the thick oxide region 3 spacing Thin Oxide 3 2 Si Gate of MOS Field Oxide Minimum gate overlap of field 2 Minimum contact to gate spacing 2 Contacts to polysilicon allowed on thick oxide only Minimum spacing to thin oxide 2 Minimum poly to thin oxide spacing Thin Oxide Field Oxide 4 2 2 2
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