Section 11 Process Integration Jaeger Chapters 9 11 EE143 Ali Javey Slide 11 1 Process Integration Self aligned Techniques LOCOS self aligned channel stop Self aligned Source Drain Lightly Doped Drain LDD Self aligned silicide SALICIDE Self aligned oxide gap MEMS Release Techniques Sacrificial Layer Removal Substrate Undercut Example IC Process Flows NMOS Generic NMOS Process Flow CMOS The MOSIS Process Flow Advance MOS Techniques Twin Well CMOS Retrograde Wells SOI CMOS EE143 Ali Javey Slide 11 2 Self aligned Source and Drain poly Si gate Perfect Alignment n As n As Off Alignment n n The n S D always follows gate EE143 Ali Javey Slide 11 3 Comment Non self aligned Alternative n n n n 1 2 Channel not linked to S D n n Solution Use gate overlap to avoid offset error Stray capacitance Disadvantages Two lithography steps excess gate overlap capacitance EE143 Ali Javey Slide 11 4 Lightly Doped Source Drain MOSFET CVD oxide spacer n n n SiO2 n p sub The n pockets LDD doped to medium conc 1E18 are used to smear out the strong E field between the channel and heavily doped n S D in order to reduce hot carrier generation EE143 Ali Javey Slide 11 5 LDD Process n implant for LDD CVD conformal deposition SiO2 CVD SiO2 SiO2 Directional RIE of CVD Oxide EE143 Ali Javey Slide 11 6 LDD Process cont d Spacer left when CVD SiO2 is just cleared on flat region 0 25 m 0 05 m n n n implant n n n EE143 Ali Javey n Slide 11 7 Salicide Integration Ti deposition Ti n n SiO2 Si heat treatment 700o C TiSi2 Ti 2Si TiSi2 Ti Ti Ti Ti will not react with SiO2 Selective etch to remove unreacted Ti only EE143 Ali Javey Slide 11 8 CMOS Basic single well process EE143 Ali Javey Slide 11 9 Single well process cont d Pattern mask opening For p well implant Shallow implantation of boron Diffusion drive in To form p well in oxidizing ambient Remove masking oxide EE143 Ali Javey Slide 11 10 Single well process cont d Pad oxide growth and CVD Si3N4 Pattern field oxide regions Blanket implant of Boron for p channel stop inside p well Protect p well regions with photoresist LOCOS Oxidationxxx Thermal oxidation of gate SiO2 EE143 Ali Javey Slide 11 11 Single well process cont d CVD poly Si Pattern poly Si gates Protect ALL n channel transistors with photoresist Boron implantation to form source drain of pchannel transistors and contacts to p well EE143 Ali Javey Slide 11 12 Single well process cont d Protect ALL p channel transistors with photoresist Arsenic implantation to form source drain of n channel transistors and contacts to nsubstrate CVD SiO2 Low temperature oxide Pattern and etch contact openings to source drain well contact and substrate contact EE143 Ali Javey Slide 11 13 Single well process cont d Metal 1 deposition Pattern and etch Metal 1 interconnects CVD SiO2 EE143 Ali Javey Slide 11 14 Single well process cont d Pattern and etch contact openings to Metal 1 Metal 2 deposition Pattern and etch Metal 2 interconnects EE143 Ali Javey Slide 11 15 Twin well CMOS Technology EE143 Ali Javey Slide 11 16 Shallow Trench Isolation Shallow trench isolation in a twinwell process Intercepts depletion layers permitting tighter spacing Reduces the chance of latchup EE143 Ali Javey Slide 11 17 MEMS Diaphram Formation Diaphrams formed by anisotropic backside etching of the silicon wafer a SiO2 layer diaphram used as an etch stop b Buried SiO2 or p layer can be used as an etch stop to form thin diaphrams c Often used in pressure sensors EE143 Ali Javey Slide 11 18 MEMS Sealed Cavity Formation EE143 Ali Javey Slide 11 19 Surface Micromachining Rotary Structures EE143 Ali Javey Slide 11 20 MEMS Hinge Formation EE143 Ali Javey Slide 11 21
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