EE143 – Ali Javey Slide 11-1Section 11: Process IntegrationJaeger Chapters 9, 11EE143 – Ali JaveyProcess IntegrationExample IC Process Flows• NMOS - Generic NMOS Process Flow• CMOS - The MOSIS Process FlowSelf-aligned Techniques• LOCOS- self-aligned channel stop• Self-aligned Source/Drain• Lightly Doped Drain (LDD)• Self-aligned silicide (SALICIDE)• Self-aligned oxide gapAdvance MOS Techniques• Twin Well CMOS , Retrograde Wells , SOI CMOSMEMS Release Techniques• Sacrificial Layer Removal• Substrate UndercutSlide 11-2EE143 – Ali JaveySelf-aligned Source and Drainn+n+poly-Si gateAs+ n+n+As+Off AlignmentPerfect Alignment* The n+ S/D always follows gateSlide 11-3EE143 – Ali JaveyComment: Non self-aligned Alternative.n+n+2.n+n+Solution: Use gate overlap to avoid offset error..n+n+1Channel not linked to S/DStraycapacitanceDisadvantages: Two lithography steps, excess gate overlap capacitanceSlide 11-4EE143 – Ali Javey Slide 11-5Lightly Doped Source/Drain MOSFETThe n-pockets (LDD) doped to medium conc (~1E18) are used to smear out the strong E-field between the channel and heavily doped n+ S/D, in order to reduce hot-carrier generation.n+n+nnSiO2CVD oxidespacerp-subEE143 – Ali Javey Slide 11-6LDD Processn implantfor LDDSiO2CVD SiO2Directional RIE of CVD OxideCVD conformaldeposition SiO2EE143 – Ali Javey Slide 11-7Spacer left when CVD SiO2is just cleared on flat region.nn0.05μm0.25μmn+n+n+implantnnLDD Process (cont’d)EE143 – Ali Javey Slide 11-8n+n+SiO2TiTi depositionSiTiTiSi2TiTiSelective etch to remove unreacted Ti only.2)700(22SiOwithreactnotwillTiTiSiSiTiCtreatmentheato→+>Salicide IntegrationEE143 – Ali Javey Slide 11-9CMOS: Basic single-well processEE143 – Ali Javey Slide 11-10Pattern mask openingFor p-well implantShallow implantation of boronDiffusion drive-inTo form p-well in oxidizing ambientRemove masking oxideSingle-well process (cont’d)EE143 – Ali Javey Slide 11-11Pad oxide growth and CVD Si3N4.Pattern field oxide regionsBlanket implant of Boron for p channel stop inside p-wellProtect p-well regions with photoresist.LOCOS OxidationxxxThermal oxidation of gate SiO2Single-well process (cont’d)EE143 – Ali Javey Slide 11-12Pattern poly-Si gatesProtect ALL n-channel transistors with photoresist.Boron implantation to form source/drain of p-channel transistors and contacts to p-wellCVD poly-Si !!Single-well process (cont’d)EE143 – Ali Javey Slide 11-13Protect ALL p-channeltransistors with photoresist.CVD SiO2(Low-temperature oxide)Pattern and etch contact openings to source/drain, well contact, and substrate contact.Arsenic implantation to form source/drain of n-channel transistors and contacts to n-substrateSingle-well process (cont’d)EE143 – Ali Javey Slide 11-14Metal 1 depositionPattern and etch Metal 1 interconnectsCVD SiO2Single-well process (cont’d)EE143 – Ali Javey Slide 11-15Pattern and etch contact openings to Metal 1.Metal 2 deposition. Pattern, and etch Metal 2 interconnects.Single-well process (cont’d)EE143 – Ali Javey Slide 11-16Twin-well CMOS TechnologyEE143 – Ali Javey Slide 11-17Shallow Trench Isolation• Shallow trench isolation in a twin-well process• Intercepts depletion layers permitting tighter spacing• Reduces the chance of latchupEE143 – Ali Javey Slide 11-18MEMS - Diaphram FormationDiaphrams formed by anisotropic backside etching of the silicon wafer (a) SiO2layer/diaphram used as an etch stop(b) Buried SiO2or p+layer can be used as an etch stop to form thin diaphrams(c) Often used in pressure sensorsEE143 – Ali Javey Slide 11-19MEMS - Sealed Cavity FormationEE143 – Ali Javey Slide 11-20Surface Micromachining - Rotary StructuresEE143 – Ali Javey Slide 11-21MEMS - Hinge
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