Section 10 Layout Jaeger Chapter 9 EE143 Ali Javey Slide 10 1 Design Rules Interface between designer and process engineer Guidelines for constructing process masks Unit dimension Minimum line width scalable design rules lambda parameter absolute dimensions micron rules EE143 Ali Javey Slide 10 2 Layout Design Rules 1 Absolute Value Design Rules Use absolute distances 2 based Design Rules EE143 Ali Javey Slide 10 3 3 Metal Si Contact Hole same rule for Metal poly 2 2 Min contact hole 2 x 2 Min contact hole to diffusion layer distance n Al SiO2 p sub EE143 Ali Javey n SiO2 p sub Slide 10 4 Metal Lines Min width 2 Line 1 Min metal metal spacing 3 3 2 Line 2 Rationale metal runs on rough topography 3 spacing to ensure no shorting between the 2 lines EE143 Ali Javey Slide 10 5 M1 Contact Overlap Min overlap of contact hole Etching problem SiO2 CVD SiO2 deposition problem in narrow gap Si EE143 Ali Javey Slide 10 6 Poly Si Gate Min gate overlap of field oxide 2 2 Avoid n channel formation during S D Implant n n n ideal With overlay error EE143 Ali Javey Slide 10 7 Gate contacting Comment Al to poly contact should not be directly on top of gate oxide area Gate oxide Al Poly gate Si Al Al 400OC Al spike Poly SiO2 Si Poly SiO2 Si EE143 Ali Javey Slide 10 8
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