EE143 –Ali Javey Slide 10-1Section 10: LayoutJaeger, Chapter 9Design Rules• Interface between designer and process engineer• Guidelines for constructing process masks• Unit dimension: Minimum line width» scalable design rules: lambda parameter» absolute dimensions (micron rules)EE143 –Ali Javey Slide 10-2EE143 –Ali JaveyLayout Design Rules(1) Absolute-Value Design Rules* Use absolute distances (2) λ -based Design Rules3Slide 10-3EE143 –Ali JaveyMetal-Si Contact Holeλ2λλMin. contact hole = 2 λ x 2 λλ2Min contact hole to diffusionlayer distance = λn+p-subSiO2n+p-subSiO2Al(same rule for Metal-poly)λSlide 10-4EE143 –Ali JaveyMetal LinesMin. metal-metalspacing = 3λλ3λ2Line2Line1[Rationale]metal runs on rough topography3 λ spacing to ensure no shorting between the 2 lines.Min width = 2λSlide 10-5EE143 –Ali JaveyMin overlap of contact hole = λλλSiEtchingproblemCVD SiO2deposition.problem innarrow gapλSiO2M1-Contact OverlapSlide 10-6EE143 –Ali JaveyPoly-Si Gaten+n+n+Min gate-overlap offield oxide =λ2λ2Avoid n+ channel formation during S/D ImplantidealWith overlay errorSlide 10-7EE143 –Ali JaveyAlPolySiO2Si~400OCAlPolySiO2SiAlspikeAlPoly gateComment:Al to poly contactshould not be directly on topof gate oxide areaSiGate oxideGate contactingSlide
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