EE 143 MICROFABRICATION TECHNOLOGY SPRING 2010 C. Nguyen PROBLEM SET #2 Issued: Thursday, Feb 4, 2010 Due: Thursday, Feb. 11, 2010, 7:00 p.m. in the EE 143 homework box in 240 Cory I. Process Flow/Layout to Cross-Section 1. Consider the cross-section of a device shown below: a. What kind of device is this? b. Generate a possible process flowchart for fabrication of this structure. Use a form like the cross-sections in Figure 1.6 in Jaeger’s textbook. n+P-substrateAlAlSiO2p+ 2. Consider the following layout of two MOSFET devices and the corresponding process flow: Device BWWLLLLAA’MetalContactActive Poly-SiDevice AN-well P+/N+EE 143 MICROFABRICATION TECHNOLOGY SPRING 2010 C. Nguyen The process flow 1) Silicon oxidation: target = 300nm 2) Lithography: Mask I (N-well) 3) Etch SiO2 4) Remove PR 5) N-well diffusion: P (n-type) 6) Etch SiO2 7) Silicon oxidation: target = 100nm 8) LPCVD Si3N4: target = 500nm 9) Lithography: Mask II (Active) 10) Etch Si3N4 11) Etch SiO2 12) Field isolation implant: B+ (p-type) 13) Remove PR 14) Grow 1μm of SiO2 thermally (LOCOS oxidation) 15) Etch Si3N4 16) Etch SiO2 17) Dry oxidation for gate oxide: target = 100nm 18) LPCVD situ phosphorous-doped gate polysilicon: target = 350nm 19) Lithography: Mask III (Poly) 20) Dry etch polysilicon 21) Remove PR 22) Lithography: Mask IV (n+ implant)(dark field) 23) D/S ion implantation: P (n-type) 24) Remove PR 25) Lithography: Mask V (p+ implant)(clear field) 26) D/S ion implantation: B (p-type) 27) Remove PR 28) Anneal at 1050°C to activate dopants and drive-in diffusion 29) LPCVD PSG: target = 1 μm and reflow at 950°C 30) Lithography: Mask VI (contact) 31) Etch SiO2 down to S/D regions 32) Remove PR 33) Deposit Al: sputtering target = 1 μm 34) Lithography: Mask VII (metal) 35) Dry etch Al a. Plot the cross-sections along AA’ plane through step 6), 14), 21), 26) and 35). b. A MOSFET device can be represented by a circuit symbol view, e.g., a NMOS device layout can be depicted as: WLWL Draw the circuit schematics implemented by each device layout in A and B. Then, for each of A and B, equate the circuit to an equivalent single device and redraw the layout so that it realizes the corresponding single
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