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Berkeley ELENG 143 - Homework Assignment

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N.CHEUNG EE143, Fall 2010 Homework Assignment # 9 (Due November 5, Fri , 9am) Reading Assignment 1)EE143 Lecture Notes on Process Integration 2) Jaeger, pp.221-228 on CMOS integration 3) REPRINT on Bspace : Sections of Maly , Atlas of IC Technology – narrative description of CMOS process flows In this homework assignment, we will practice designing process flows based on planar technology. You have to describe the process flow and to draw cross-sections of the devices at key processing steps. Problem 1 Generic NMOS Process Flow Draw the cross-sections of the NMOS device along the lines (i) A-A and (ii) B-B after (a) The silicon nitride CVD deposition step (b) The field oxide growth step (c) RIE poly-Si gate step (d) RIE of intermediate oxide and thermal oxide step (e) Hydrogen annealing step. A ABBProblem 1 process flow description SubstrateBoron doped (100)SiResistivity= 20 -cmThermal Oxidation~100Å pad oxideCVD Si3N4~ 0.1 umLithographyPattern Field OxideRegionsRIE removal of Nitride and pad oxideChannel StopImplant: 3x1012B/cm260keVThermal Oxidation to grow 0.45um oxideWet EtchNitrdie and pad oxideIon Implant forThresholdVoltage control8x1011B/cm235keVThermal OxidationTo grow 250Ågate oxideLPCVDPoly-Si~ 0.35umDope Poly-Si to n+with PhosphorusDiffusion sourceSubstrateBoron doped (100)SiResistivity= 20 -cmThermal Oxidation~100Å pad oxideCVD Si3N4~ 0.1 umLithographyPattern Field OxideRegionsRIE removal of Nitride and pad oxideChannel StopImplant: 3x1012B/cm260keVThermal Oxidation to grow 0.45um oxideWet EtchNitrdie and pad oxideIon Implant forThresholdVoltage control8x1011B/cm235keVThermal OxidationTo grow 250Ågate oxideLPCVDPoly-Si~ 0.35umDope Poly-Si to n+with PhosphorusDiffusion sourceLithographyPoly-Si Gate patternRIE Poly-Si gateSource /Drain Implantation~ 1016As/cm280keVThermal OxidationGrow ~0.1um oxide on poly-SiAnd source/drianLPCVDSiO2~0.35umLithographyContact Window patternRIE removal of CVD oxide and thermal oxideSputter DepositAl metal~0.7umLithographyAl interconnect patternRIE etch of Al metallizationSintering at ~400oC in H2 ambientto improve contact resistanceand to reduce oxide interface chargeLithographyPoly-Si Gate patternRIE Poly-Si gateSource /Drain Implantation~ 1016As/cm280keVThermal OxidationGrow ~0.1um oxide on poly-SiAnd source/drianLPCVDSiO2~0.35umLithographyContact Window patternRIE removal of CVD oxide and thermal oxideSputter DepositAl metal~0.7umLithographyAl interconnect patternRIE etch of Al metallizationSintering at ~400oC in H2 ambientto improve contact resistanceand to reduce oxide interface chargeProblem 2 Double Poly DRAM Design a process flow for the following double poly-Si NMOS dynamic random access memory (DRAM) element. Note that 1st poly and 2nd poly are separated a very thin layer of thermal oxide. A standard NMOS process is used with LOCOS to form the field oxide. Enter the process description under the first column and a sketch of the cross-section after critical process steps under the Second column. ppp -substrate (lightly doped)n+SiO2 (Field Oxide)SiO2CVD SiO2SiO21st poly2nd polythermal oxidesAlAl (wordline)NMOSFETMOSCapacitorn+ Si (bitline)1st polyp-substrate2nd polyChannel stopppp -substrate (lightly doped)n+SiO2 (Field Oxide)SiO2CVD SiO2SiO21st poly2nd polythermal oxidesAlAl (wordline)NMOSFETMOSCapacitorn+ Si (bitline)1st polyp-substrate2nd polyChannel stopProblem 3 RC Filter Integration We would like to implement a simple RC low-pass filter in integrated form. The top view, the equivalent circuit, and the cross-section along line AB are shown below. The resistor body is lightly doped (n-) poly-Si and the top capacitor plate of is heavily doped (n+) poly-Si . Cross-sections along AB after major processing steps are sketched in the right column of the table shown below. Fill in the sequence of process steps used in the left column. Process Description Cross Section along AB 1) Starting wafer, p- Si p -substrate (lightly doped) n- poly Si (lightly doped)ppp -substrate (lightly doped)n+SiO2SiO2CVD SiO2n+ poly Si (heavily doped)AlGate oxideA BAlAl n+ Si(bottom plate of capacitor)n+ poly Si (top plate of capacitor) n- poly Sicontact holeAlProblem 4 Gate-Last MOSFET After aluminum deposition, the processing temperature cannot higher than 650°C because the aluminum will melt. For example, the 900°C annealing step required to activate the implanted dopants for source/drain implants cannot be performed after aluminum deposition. With this constraint in mind, design a process flow for this self-aligned implanted source/drain MOSFET using Al as the gate material [shown as Al(level 1) in figure]. A schematic cross-section of the device is illustrated below. Describe the process flow and show the cross-sections at major processing steps. [Hint: Use a high-temperature compatible material to form a “dummy” gate. After S/D formation, selectively remove the dummy gate and replace it with Al ] CVD SiO2p pSiO2 SiO2Al (level 2)p- substraten+ n+Al (level 1)Self-aligned Al-Gate MOSFETProblem 5 Sub-50nm MOSFET Process Flow Optical lithography can only define features larger than 50nm. To fabricate MOSFETs with channel length less than 50nm, the following process description is found in a publication: (1) Fabricate oxide trench for device isolation (2) Form silicon nitride on pad-oxide films. (3) Pattern nitride/pad-oxide to smallest feature by optical lithography (4) n+ S/D implant (5) Angle implant (tilted ~ 45 degrees ) to form n+ pockets. (6) Form TiSi2 on S/D regions (7) Deposit CVD oxide and planarize surface by CMP (8) Selectively remove nitride dummy gate (9) Deposit CVD oxide and form oxide spacer by RIE (10) Grow gate oxide by thermal oxidation (11) Poly-Si gate deposition by CVD (12) Pattern Poly-Si gate The final device cross-section is illustrated below. Let us start with a structure with oxide trench isolation already fabricated. Continue the process description with your interpretation of the process flow. Show the cross-sections at major processing steps. Process Description Cross-section 1) Starting structure ( oxide trench isolation) SiO2SiO2p-Si SiO2CVD oxideSiO2CVD oxiden+n+n+n+poly-SigateThermalgate oxideOxide spacerAngledImplantn+ pocketNormalS/D implantSmallest featureprintable byoptical


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Berkeley ELENG 143 - Homework Assignment

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