N CHEUNG EE143 Fall 2010 Homework Assignment 9 Due November 5 Fri 9am Reading Assignment 1 EE143 Lecture Notes on Process Integration 2 Jaeger pp 221 228 on CMOS integration 3 REPRINT on Bspace Sections of Maly Atlas of IC Technology narrative description of CMOS process flows In this homework assignment we will practice designing process flows based on planar technology You have to describe the process flow and to draw cross sections of the devices at key processing steps Problem 1 Generic NMOS Process Flow Draw the cross sections of the NMOS device along the lines i A A and ii B B after a The silicon nitride CVD deposition step b The field oxide growth step c RIE poly Si gate step d RIE of intermediate oxide and thermal oxide step e Hydrogen annealing step B A A B Problem 1 process flow description Substrate Boron doped 100 Si Resistivity 20 cm Thermal Oxidation 100 pad oxide CVD Si3N4 0 1 um Lithography Pattern Field Oxide Regions RIE removal of Nitride and pad oxide Channel Stop Implant 3x1012 B cm2 60keV Thermal Oxidation to grow 0 45um oxide Wet Etch Nitrdie and pad oxide Ion Implant for Threshold Voltage control 8x1011 B cm2 35keV Thermal Oxidation To grow 250 gate oxide LPCVD Poly Si 0 35um Dope Poly Si to n with Phosphorus Diffusion source Lithography Poly Si Gate pattern RIE Poly Si gate Source Drain Implantation 1016 As cm2 80keV Thermal Oxidation Grow 0 1um oxide on poly Si And source drian LPCVD SiO2 0 35um Lithography Contact Window pattern RIE removal of CVD oxide and thermal oxide Sputter Deposit Al metal 0 7um Lithography Al interconnect pattern RIE etch of Al metallization Sintering at 400oC in H2 ambient to improve contact resistance and to reduce oxide interface charge Problem 2 Double Poly DRAM Design a process flow for the following double poly Si NMOS dynamic random access memory DRAM element Note that 1st poly and 2nd poly are separated a very thin layer of thermal oxide A standard NMOS process is used with LOCOS to form the field oxide Enter the process description under the first column and a sketch of the cross section after critical process steps under the Second column thermal oxides Al 1st poly CVD SiO2 2nd poly SiO2 SiO2 n SiO2 Field Oxide p p Channel stop p substrate lightly doped Al wordline 2nd poly n Si bitline p substrate 1st poly NMOS FET MOS Capacitor Problem 3 RC Filter Integration We would like to implement a simple RC low pass filter in integrated form The top view the equivalent circuit and the cross section along line AB are shown below The resistor body is lightly doped n polySi and the top capacitor plate of is heavily doped n poly Si Cross sections along AB after major processing steps are sketched in the right column of the table shown below Fill in the sequence of process steps used in the left column n Si bottom plate of capacitor Al Al n poly Si A contact hole B Al n poly Si lightly doped Al SiO2 n poly Si top plate of capacitor n poly Si heavily doped Gate oxide CVD SiO2 SiO2 n p p p substrate lightly doped Process Description 1 Starting wafer p Si Cross Section along AB p substrate lightly doped Problem 4 Gate Last MOSFET After aluminum deposition the processing temperature cannot higher than 650 C because the aluminum will melt For example the 900 C annealing step required to activate the implanted dopants for source drain implants cannot be performed after aluminum deposition With this constraint in mind design a process flow for this self aligned implanted source drain MOSFET using Al as the gate material shown as Al level 1 in figure A schematic cross section of the device is illustrated below Describe the process flow and show the cross sections at major processing steps Al level 1 Al level 2 CVD SiO2 SiO2 n n SiO2 p p p substrate Self aligned Al Gate MOSFET Hint Use a high temperature compatible material to form a dummy gate After S D formation selectively remove the dummy gate and replace it with Al Problem 5 Sub 50nm MOSFET Process Flow Optical lithography can only define features larger than 50nm To fabricate MOSFETs with channel length less than 50nm the following process description is found in a publication 1 Fabricate oxide trench for device isolation 2 Form silicon nitride on pad oxide films 3 Pattern nitride pad oxide to smallest feature by optical lithography 4 n S D implant 5 Angle implant tilted 45 degrees to form n pockets 6 Form TiSi2 on S D regions 7 Deposit CVD oxide and planarize surface by CMP 8 Selectively remove nitride dummy gate 9 Deposit CVD oxide and form oxide spacer by RIE 10 Grow gate oxide by thermal oxidation 11 Poly Si gate deposition by CVD 12 Pattern Poly Si gate The final device cross section is illustrated below Smallest feature printable by optical lithography Oxide spacer poly Si gate CVD oxide n SiO2 Normal S D implant CVD oxide n n n SiO2 Angled Thermal Implant gate oxide n pocket Let us start with a structure with oxide trench isolation already fabricated Continue the process description with your interpretation of the process flow Show the cross sections at major processing steps Process Description Cross section 1 Starting structure oxide trench isolation SiO2 SiO2 p Si
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