Undergraduate IC MEMS Processing Laboratory Introduction and History The EECS 143 undergraduate course Processing and Design of Integrated Circuits has been designed to familiarize students with fabrication technology types of device structures electrical characterization modeling of devices and with the relationships between physical layout and electrical characteristics The course was first offered in 1972 by Professor D A Hodges as a graduate course It was changed into an undergraduate class the following year and joined with an independent laboratory course EE134 started several years earlier 1968 by Professors W G Oldham and W Howard When the two courses were joined the laboratory section was revised from the fabrication of bipolar devices to PMOS transistors and other test structures EE147 In 1980 when the Microfabrication Research Facility was designed the undergraduate laboratory served as a test site for the modular construction planned for the research lab As a result two smaller clean room areas separated by a service chase were built into the existing large room and advanced processing equipment was installed At the same time a new process was developed and introduced in 1981 The quarter system allowed only 10 three hour laboratory sessions to complete the processing and to characterize the devices thus a simple 4 mask aluminum gate NMOS process was designed with spin on doping for source and drain diffusions and metal definition by lift off EECS 143 has been offered every semester since its inception and became a popular course not only for undergraduates but also for those graduate students who are involved in process technology integrated circuits design and processing When the campus changed from the quarter to the semester system the number of laboratory sessions increased to 15 and it was possible to carry out a more detailed characterization of the test chip Advanced test equipment was obtained over the years and by this time following Berkeley s tradition of constant updating of courses it was also appropriate to change the process to reflect current industry standards more closely Thus both the process and test chip were redesigned and the new chip was introduced during the Fall semester of 1987 which replaced aluminum gates with self aligned polysilicon gates In 1995 the layout was redesigned with more robust devices And due to the high interest of MEMS devices the layout has been revised again in 2000 Four MEMS structure have been added to the EE143 mask set A thermal bimorph actuator a heat platform a cantilever and a campanile These four are intended to be representative of the types of structures being used by the MEMS community Course Description EECS 143 Processing and Design of Integrated Circuits is a 4 credit undergraduate course given every semester with three hours of lecture and three hours of laboratory per week The course focuses on Principles and mechanisms of Microfabrication Device structure and characterization Relations between physical layout and electrical characteristics Surface micromachining technology MOS transistors and simple circuit elements are fabricated in the laboratory and electrically evaluated The MEMS structures can be activated with electrical heating The prerequisite course is EE40 Introduction to Microelectronic Circuits OR EE100 Electronic Technique to Engineering For students without Semiconductor Physics Devices background EECS 143 will provide a brief introduction to these topics Facilities An independent laboratory with an area of approximately 840 square feet is maintained for EECS 143 in 218 Cory Hall Maintenance of the processing equipment is provided by Microlab staff and of the characterization instrumentation by the EECS Electronics Support Group The equipment is arranged to provide optimum conditions in which a group of 8 students can operate each pair processing one wafer There are essentially three working areas two of which are maintained under clean room conditions for processing 1 the photoresist clean room where resist spinning baking and alignment are done aluminum evaporator for metallization and Nanospec and four point probe where thin film thickness and sheet resistance measurement are done 2 the diffusion and etching clean room with 3 furnaces and two wet process stations for the rest of the operations 3 the characterization area with five probe stations for electrical testing with the aid of five HP 4145 Semiconductor Parameter Analyzers and a laserjet printer There are also six computers with Microsoft Windows 2000 operation system class accounts are given out at the beginning of the semester Students are required to perform process simulations using SUPREM The laboratory s equipment is listed in the attached table Test Chip Layout The test chip was laid out using the KIC graphics editor Each device was laid out as a separate cell so that they could be placed as instances once the chip was ready to be assembled This facilitated a compact arrangement of devices on the final chip Devices with repeating structural units such as the ring oscillator were also laid out using instances of the basic unit Included on the chip were many of the test structures from the original design along with several new ones There are four main groups of structures 1 Resolution test patterns resistors and capacitors for process characterization No s 1 6 2 Diode n channel MOSFET s and lateral BJT s No s 7 13 3 Inverter NOR gate ring oscillator contact resistance for simple circuit measurements No s 14 17 4 Aluminum SiO2 Bimorph campanile cantilever array heater platform as MEMS devices No s 18 21 Process The 4 mask NMOS process starts with 3 p type wafers of 3 5 ohm cm resistivity which were blanketimplanted with boron before initial oxidation This serves as both the field and the device threshold implant which was moved to the beginning of the process to avoid delays during the semester After initial oxidation 5000 A the active n diffusion area is defined with Mask I ACTV This is followed by gate oxidation 800 A and poly silicon deposition 3500 A Mask II POLY defines the gate The poly Si is wet etched and the active area is BHF dipped clean for n diffusion taking advantage of the self aligned source drain feature of poly Si gates A spin on phosphorous silica film is used as the source for n diffusion After drive and oxidation Mask III CONT is aligned and contact openings are etched with BHF After aluminum evaporation
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