EE143 F05 Lecture 19 Layout Design Rules 1 Absolute Value Design Rules Use absolute distances 2 based Design Rules Professor N Cheung U C Berkeley 1 1 EE143 F05 Lecture 19 EE143 Layout Design Rules 1 Basic length unit 2 m 1 1 Lithography and etching limit 2 1 2 Overlay accuracy Professor N Cheung U C Berkeley 2 EE143 F05 Lecture 19 2 1 Metal Si Contact Hole same rule for Metal poly 2 2 Min contact hole 2 x 2 Min contact hole to diffusion layer distance n SiO2 p sub Professor N Cheung U C Berkeley Al n SiO2 p sub 3 EE143 F05 Lecture 19 2 2 Metal Lines Min width 2 Min metal metal spacing 3 Rationale Line 1 3 2 Line 2 metal runs on rough topography 3 spacing to ensure no shorting between the 2 lines Professor N Cheung U C Berkeley 4 EE143 F05 Lecture 19 Min overlap of contact hole SiO2 Etching problem CVD SiO2 deposition problem in narrow gap Si Professor N Cheung U C Berkeley 5 EE143 F05 Lecture 19 Metal line width is larger when running over a contact hole 2 2 4 Configuration 1 Configuration 2 2 Professor N Cheung U C Berkeley 6 EE143 F05 Lecture 19 2 3 Poly Si Lines Min width 2 2 Line 1 Min poly poly spacing 2 2 Line 2 Rationale Unlike metal lines poly Si runs on smoother topography metal poly Min underlap of metal poly contact 4 4 Professor N Cheung U C Berkeley 7 EE143 F05 Lecture 19 Example Metal Contact to Poly metal poly Note Both metal and poly linewidths will enlarge to accommodate contact hole overlay error Professor N Cheung U C Berkeley 8 EE143 F05 Lecture 19 2 4 MOS Thin Oxide Region Thick Oxide Region FOX Min Width 2 Thin Oxide Region active device area 2 2 Min spacing 3 3 2 Professor N Cheung U C Berkeley 9 EE143 F05 Lecture 19 Min underlap of thin oxide contact Professor N Cheung U C Berkeley 10 EE143 F05 Lecture 19 3 Poly Si Gate Min gate overlap of field oxide 2 2 Comment Avoid n channel formation during S D Implant n n ideal Professor N Cheung U C Berkeley n With overlay error 11 EE143 F05 Lecture 19 Min thin oxide contact to gate spacing 2 2 Professor N Cheung U C Berkeley 2 12 EE143 F05 Lecture 19 Comment Al to poly contact should not be directly on top of gate oxide area Al Poly gate Gate oxide Si Al Poly SiO2 Si Professor N Cheung U C Berkeley 400OC Al Al spike Poly SiO2 Si 13 EE143 F05 Lecture 19 Al contact on thick oxide area ok 2 SiO2 CVD FOX Professor N Cheung U C Berkeley 14 EE143 F05 Lecture 19 Min Gate Width 2 Min Gate Length 2 Usually W L are specified by circuit requirement Min poly to thin oxide spacing Professor N Cheung U C Berkeley 15 EE143 F05 Example Lecture 19 Design a minimum size poly gate MOS transistor with W L 4 m 4 m 2 x 2 Half way distance to next MOSFET 1 5 Minimum size contact 2 x2 Minimum thin oxide region underlap of contact Minimum source drain contact to gate spacing 2 Minimum L 2 Minimum W 2 Minimum gate overlap of field oxide region 2 Minimum metal overlap of contact Minimum thin oxide region to thin oxide region spacing 3 Layout area transistor 15 x7 105 2 Professor N Cheung U C Berkeley metal poly Active region Contact hole 16
View Full Document
Unlocking...