1Professor N Cheung, U.C. BerkeleyLecture 19EE143 F05Layout Design Rules(1) Absolute-Value Design Rules* Use absolute distances (2) λ -based Design Rules12Professor N Cheung, U.C. BerkeleyLecture 19EE143 F05EE143 Layout Design Rules1. Basic length unit = λ = 2µm1.2 Overlay accuracy = λ1.1 Lithography and etching limit =2λ3Professor N Cheung, U.C. BerkeleyLecture 19EE143 F052.1 Metal-Si Contact Holeλ2λλMin. contact hole = 2 λ x 2 λλ2Min contact hole to diffusionlayer distance = λn+p-subSiO2n+p-subSiO2Al(same rule for Metal-poly)λ4Professor N Cheung, U.C. BerkeleyLecture 19EE143 F052.2. Metal LinesMin. metal-metalspacing = 3λλ3λ2Line2Line1[Rationale]metal runs on rough topography3 λ spacing to ensure no shorting between the 2 lines.Min width = 2λ5Professor N Cheung, U.C. BerkeleyLecture 19EE143 F05Min overlap of contact hole = λλλSiEtchingproblemCVD SiO2deposition.problem innarrow gapλSiO26Professor N Cheung, U.C. BerkeleyLecture 19EE143 F05Metal line-width is larger when runningover a contact holeλλ2λλ4λ22λλλConfiguration 1Configuration 27Professor N Cheung, U.C. BerkeleyLecture 19EE143 F052.3 Poly-Si LinesMin width = 2λMin poly-poly spacing = 2 λMin underlap of metal/poly contact = λλ2λ2Line 2λλλλ44×polymetalLine 1[Rationale: Unlike metal lines, poly-Si runs on smoother topography]8Professor N Cheung, U.C. BerkeleyLecture 19EE143 F05λλpolymetalExample: Metal Contact to PolyNote:Both metal and poly linewidthswill enlarge to accommodatecontact hole overlay error λ9Professor N Cheung, U.C. BerkeleyLecture 19EE143 F052.4. MOS Thin-Oxide RegionMin spacing = 3 λThick Oxide Region (FOX)Thin Oxide Region(active device area)λ2λ2λ2λ3Min Width = 2 λ10Professor N Cheung, U.C. BerkeleyLecture 19EE143 F05Min underlap of thin-oxide contact = λλλ11Professor N Cheung, U.C. BerkeleyLecture 19EE143 F053. Poly-Si Gaten+n+n+Min gate-overlap offield oxide =λ2[Comment]λ2Avoid n+ channel formation during S/D ImplantidealWith overlay error12Professor N Cheung, U.C. BerkeleyLecture 19EE143 F05Min thin-oxide contact to gate spacing = 2 λ2 λ2 λ13Professor N Cheung, U.C. BerkeleyLecture 19EE143 F05AlPolySiO2Si~400OCAlPolySiO2SiAlspikeAlPoly gateComment:Al to poly contactshould not be directly on topof gate oxide areaSiGate oxide14Professor N Cheung, U.C. BerkeleyLecture 19EE143 F05SiO2 (CVD)FOXλ2Al contact on thick oxide area ok15Professor N Cheung, U.C. BerkeleyLecture 19EE143 F05Min Gate Width = 2 λMin Gate Length = 2 λ}Usually: W/L are specified by circuit requirement.Min. poly to thin oxide spacing = λλ16Professor N Cheung, U.C. BerkeleyLecture 19EE143 F05Design a minimum-size poly-gate MOS transistor with W/L = 4µm/4µm (2 λ x 2λ )ExampleMinimum size contact = 2λx2λMinimum thin-oxide-region underlap of contact = λMinimum source/drain contact to gate spacing = 2λMinimum L = 2λ Minimum W = 2λMinimum gate overlap of field-oxide region = 2λMinimum metal overlap of contact = λMinimum thin-oxide-region to thin-oxide-region spacing = 3λ* Layout area /transistor = 15λx7λ = 105 λ2metalpolyActive regionContact holeHalf-waydistance tonext MOSFET( = 1. 5 λ
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