EE143 F05 Lecture 2 Czochralski Crystal Growth Crystal Pulling Shaping and Polishing Professor N Cheung U C Berkeley Crystal Ingots 300 mm wafer 1 EE143 F05 Lecture 2 Advantage of larger diameter wafers Wafer area larger Chip area larger Professor N Cheung U C Berkeley 2 EE143 F05 Lecture 2 Large Diameter Wafer Handling La Vals Fab 300mm wafer vs pizza Production Fab Overhead rail transport of wafer cassette Lateral uniformity of processing effects across the WHOLE wafer is key consideration for microfabrication design Professor N Cheung U C Berkeley 3 EE143 F05 Lecture 2 Microstructure of Electronic Materials Amorphous materials Professor N Cheung U C Berkeley Single Crystal Material 4 EE143 F05 Lecture 2 Photolithography glass plate chromium Positive Resist Part exposed to light will be dissolved in development solution Processing Temperature Ambient Professor N Cheung U C Berkeley 5 EE143 F05 Lecture 2 Etching Pattern resist mask Etching thin film Etching completed Remove resist mask Anisotropic Processing Temperature e g Reactive Ion Etching Ambient Professor N Cheung U C Berkeley Isotropic e g Wet Etching 6 EE143 F05 Lecture 2 Etching Selectivity Example HF solution etches SiO2 but not Si SiO2 Si HF solution Si A high etching selectivity is usually desired Professor N Cheung U C Berkeley 7 EE143 F05 Lecture 2 Anisotropic Wet Etching of Si Crystals Etchants KOH or EDP Ethylene Diamine Pyrocatechol Cross section Top view 100 Si substrate Etching stops Etching continues Professor N Cheung U C Berkeley Effect of different mask opening 8 EE143 F05 Thermal Oxidation Lecture 2 Processing Temperature 900 1100 oC Si O2 SiO2 Si 2 H2O SiO2 2H2 Oxide Xox thickness t t O2 or H2O diffuses through SiO2 and reacts with Si at the interface to form more SiO2 1 m of SiO2 formed consumes 0 44 m of Si substrate Thin oxide growth e g gate oxide use O2 Dry oxidation Thick oxide growth e g field oxide use H2O Wet oxidation Oxidation time t Professor N Cheung U C Berkeley 9 EE143 F05 Lecture 2 Uneven surface topography with window oxidation 1st oxidation SiO2 Si Si Realistic topography with 2 dimensional effect SiO2 Si Pattern oxide window by litho and etch 2nd oxidation SiO2 SiO2 Si Si Note uneven Si surface after window oxidation Professor N Cheung U C Berkeley 10 EE143 F05 Lecture 2 Local Oxidation silicon nitride O2 Si3N4 pad oxide 100 A Si Thermal Oxidization LOCOS Process nitride SiO2 Si Professor N Cheung U C Berkeley 11 EE143 F05 Ion Implantation Lecture 2 typically used to introduce dopans into semiconductors Ion Energy 1 keV to 200 keV Processing Temperature Room temp during implantation After implantation a 900oC 1000oC anneal step is needed to 1 activate dopants 2 restore Si crystallinity Professor N Cheung U C Berkeley 12 EE143 F05 Lecture 2 Diffusion To introduce dopants into semiconductors Predeposition To spread out the dopant profile Drive in D D0 e Q kT D Diffusion Constant Q Activation Energy T Temp in K D as T Processing Temperature 950 1200 oC Professor N Cheung U C Berkeley 13 EE143 F05 Lecture 2 Predeposition Si surface concentration maintained at constant Cs solid solubility during predep Dose of dopant incorporation Cs 2 Dt Professor N Cheung U C Berkeley 14 EE143 F05 Lecture 2 Predeposition and Drive in Half gaussian depth profile after long drive in Predep only Dopant dose conserved during drive in Diffusion distance Dt Predep Drive in Concentration versus Depth Professor N Cheung U C Berkeley 15 EE143 F05 Lecture 2 Physical Vapor Deposition 1 Evaporation Deposition Si Substrate Substrate at room temp Deposited Al film polycrystalline evaporation Al charge Tsource Tboiling of Al 700OC Professor N Cheung U C Berkeley 16 EE143 F05 Lecture 2 Physical Vapor Deposition 2 Sputtering Deposition Si Substrate Substrate at room temp Deposited Al film polycrystalline Ar Ar ions with keV kinetic energy Professor N Cheung U C Berkeley Al atoms ejected due to Ar ion bombardment Al target 17 EE143 F05 Lecture 2 Chemical Vapor Deposition CVD Processing Temperature 300 600oC Professor N Cheung U C Berkeley 18 EE143 F05 Lecture 2 Epitaxial Growth Processing Temperature 950 1150oC Requires an ultra clean Si surface prior to epi growth Requires deposition of Si at very high temperature for perfect crystallinity Professor N Cheung U C Berkeley 19 EE143 F05 Lecture 2 Epitaxial Growth 1 In situ surface cleaning Si Epi layer Si substrate Si substrate 2 Si CVD at high temperature Typically used when we need a lightly doped singlecrystal Si layer on top of heavily doped substrate Example n Si 1015 cm3 n Si e g 1020 cm3 Professor N Cheung U C Berkeley 20 EE143 F05 Lecture 2 Cost of Silicon Real Estate 200mm Si wafer 80 0 25 cm2 Professor N Cheung U C Berkeley 200mm Epi wafer 140 0 44 cm2 1812 sq ft House Menlo Park CA 944 492 0 56 cm2 21 EE143 F05 Lecture 2 Chemical Mechanical Polishing CMP Wafer is polished using a slurry containing silica abrasives 10 90 nm particle size etching agents e g dilute HF Backing film provides elasticity between carrier and wafer Polishing pad made of polyurethane with 1 m perforations rough surface to hold slurry Professor N Cheung U C Berkeley Ambient Temperature 22 EE143 F05 Lecture 2 Metal Plating ambient temp Professor N Cheung U C Berkeley 23 EE143 F05 Lecture 2 List of Conventional Microfabrication Modules Lithography Thermal Oxidation Etching Chemical Plasma Ion Implantation Diffusion Physical Vapor Deposition PVD Chemical Vapor Deposition CVD and Epitaxial Growth Chemical Mechanical Polishing CMP Metal Plating Professor N Cheung U C Berkeley 24 Resist Reflow Professor N Cheung U C Berkeley i 1400 1200 1000 800 600 400 200 0 Ep es is tE xp R os es ur is e tS Ev pi ap nR es or on a i Sp tion st B ak ut D te e e rin po si g tio D ep n os iti on Po Io n st C Im Im VD pl pl an an ta ta tio T h tio n n er A m al nne O D xi al op an dat t D ion iff us io n R Proce s s Te m pe rature in C EE143 F05 Lecture 2 Processing Temperature and Material Failure Temperature Si Melting Point 1412C Al Si Eutectic 560C 25 EE143 F05 Lecture 2 Interesting Facts about Chip Manufacturing A typical 2 gram silicon chip requires 1 6 kilograms of fossil fuel 72 grams of chemicals and 32 kilograms of water to manufacture To make the high grade silicon needed for the chips requires 160 times the energy used to produce raw silicon This accounts for about half of the total energy used by the chip Only a quarter is consumed during its processing life Because a chip s components are so tiny and
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