Fall 2005 6.012 Microelectronic Devices and Circuits Prof. J. A. del AlamoOptical Receiver Design ProjectNovember 18, 2005Due: December 6, 2005 on the(no later than 12:55PM)(late project reports not accepted)1. OverviewThe explosive growth in data co mmunications has stimulated the development of optical systemsfor high channel capacity (typically 4-16 channels) and high bandwidth. In a fiber optic system,a transmitter encodes the data in the form of laser pulses that are transmitted over a long opticalfiber. At the other end, a receiver detects the attenuated optical signal and amplifies it to digitallevels.Figure 1: Block diagram of an optical transmitter a nd receiver.A block diagram of an optical transmitter and receiver is shown in Figure 1. On the transmitter path,the data is multiplexed, encoded, and error correction bits are added. A laser driver and modulatordrive the laser diode, which transmits an optical signal over the fiber. After some loss in the fiber,the optical signal is detected at the receiver end by the photodiode. A transimpedance amplifierconverts the small photodiode current into a voltage, which is then amplified to digital levels forsubsequent dig ital signal processing. The transimpedance amplifier is also called a transresistanceamplifier in 6.012; for cultural reasons, we will stick with the transimpedance amplifier terminology.1MIT course websiteIntegration of all of the functions on either side of Figure 1 onto a single CMOS chip would savecosts, but the implementation has eluded system designers in part due to the complexity of realizinghigh-performance receiver circuits in CMOS. The goal of this design pr oject is to design a fast, highgain, low noise, and low power optical receiver in an inexpe nsive CMOS process.2. Design problem statementFigure 2 shows the schematic of the optical receiver. It consists of three CMOS stages: a tran-simpedance amplifier, a saturating or limiting amplifier, and an output driver. We describe thesethree stages next.Light creates electron-hole pairs that produce a current Ilightin the reverse-biased photodiode. Thediode can be modelled as a current source of value Ilightwhich flows in the reverse bias direction ofthe diode. Although the laser diode produces a large square wave pulse at the other end of the fiber,dispersion and loss make the diode current Ilightappear sinusoidal. This current is only guara nteedto have a peak value of about 10 µA. Depending on the system, los s in the fiber could be lowerand the peak diode current could be larger. However, to ensure proper operation for all systems,the worst-case (i.e. minimum) current must be used for the design. The receiver should operate atsp e e ds up to 1 MHz.Transimpedance(Transresistance)AmplifierLimiting(or Saturating)AmplifierOutput DriverCload=50fFOptical FiberIlightPMOS Device biasedin the linear regionused as a resistor ndioden1n2noutI1 I2 I3VDDFigure 2: Schematic of optical receiver.The first-stag e CMOS inverter I1 and feedback resisto r constitute a transimpedance amplifier thatconverts the photodiode current into a volta ge V1at node n1. A feedback resistor sets the gain of2the stage, which must be large to reduce the effects of noise in later stag e s.To set a reasonable design point you might first want to start by using a simple linear resistor anddetermine what value you could use to meet you design go als. Unfortunately, though linea r resistorscan be rea lized in silicon technology by using undope d poly for large r e sistor values, this approachconsumes a lot of area. With the knowledge of device physics that you have acquired in 6.012, inorder to minimize the co st you have decided to rea lize this resistor using a PMOS biased in the linearregion. An additional concern in this amplifier is that the gain needs to be as consta nt as p ossibleover the expe c ted range of Ilightvalues. This means that the resistor value s hould be as constant aspossible over the range of voltages at its terminals, or, in other words, as linear as possible. Powermust be minimized in this design, so no extra bias circuitry can be afforded. The PMOS device isto be connected as shown in Fig. 2 with the gate of the PMOS connected to GND and the bulkconnected to VDD. The design decision that you need to make is to size the PMO S appropriatelyto achieve the desired value of the resistor.The closed-loop small-signal gainV1Ilightof this first transimpedance amplifier nee ds to be as constantas possible over the range of Ilightvalues shown in Figure 3. You will need to derive an expressionfor this closed-loop gainV1Ilight, where V1is the voltage at node n1. Notice that s ince Ilightis small,Vdiode(the voltage at node ndiode) and V1will stay close to the midpoint of inverter I1, and I1 willbe held in the high-gain region. Thus the transistors in inverter I1 will stay in the saturation region,and the small signal model can be used over the full range of input current. For the Ilightshownin Figur e 3, V1should have a peak-to-peak amplitude of at least 0.1 Vpp(peak-to-peak voltage), asindicated in Figure 3. Fo r noise immunity, V1should be near the middle of the total voltage range.Therefore, the minimum of V1should be at 2.5 V, as indicated in Figure 3. To ensure that thephotodiode stays in reverse bias, and in an a ttempt to keep the depletion region width constant, thereverse biased diode voltage Vdiodeshould vary by no more than 10 mV peak-to-peak (10 mVpp). Tounderstand how Vdiodevaries with the input current and output voltage, you will also need to derivean expression for Vdiodeas a function of Ilightand V1.The second stage is called a limiting or saturating amplifier. This high-gain CMOS stage amplifiesthe small voltage V1. For maximum amplification, V1should be in the high gain region of inverterI2. The open-loop voltage gain of the limiting amplifier Av2should be large enough to ensure thatV1is amplified to full logic levels. To scale 0.1 Vppat node n1to 5 Vppat node n2requires a gain of50. Since the gain away from the midpoint of the inverter will be less than the maximum gain Av2,the specification is |Av2| ≥ 90.The output CMOS stage dr ives both the wire capacitance and the input capacitance of the digitalsignal processing circuits. This can be modelled as a c onstant 50 fF load capacitor. The outputdriver should be high speed to maximize the frequency at which the receiver can operate. Sincethe output will be routed to the digital side of the chip, it should
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