Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6.012 Microelectronic Devices and Circuits Spring 2009 Design Project _____________________________________________________________ This project may be worked on in groups of two. If you choose to work with a partner, turn in one report for both partners. The design process is long – start working early. 1 The Optical Converter Information can be encoded and transmitted optically. Such a data transmission system requires a decoding receiver that converts the information contained in the intensity of transmitted photons into useful electrical signals understandable by digital processors. You will be designing a converter from photons to a pulse width modulated signal to be used as the first stage of a four-state optical receiver. Our converter will generate pulses of four different widths in time, corresponding to the four light intensity levels the receiver detects. We will design for a 200MHz receiver system clock speed. The four pulses must be wide enough to allow for several clock cycles to complete in one pulse, and sufficiently distinct in width from each other for each of the four pulses to be differentiated by the next stage of the receiver, which counts the number of clock cycles within a pulse. The converter should be designed in three stages: 1. Stage 1 detects the incoming photon intensity and converts it into a current signal. A photodiode is a device that passes a current that is directly proportional to the detected light intensity. This current is used in the generation of two voltage steps, where the time delay between the two steps is a function of the photodiode current. 2. Stage 2 converts the time delayed voltage steps to a single pulse, whose pulse width is the time delay between the two outputs from Stage 1. 3. Stage 3 is an output buffer that is designed to drive a 5pF load capacitance. As electronics trend ever smaller and more portable, die area has become an increasingly important design parameter for circuit designers. In this project, we will focus our design efforts on minimizing total gate area while preserving desired functionality.2 Implementation 2.1 STAGE 1 We will model the photodiode in our circuit as an ideal four level current source that sources Ilight = 0µA, 1µA, 2µA, and 3µA, with 0µA corresponding to a completely dark input. A bias current source of Ibias = 2µA is placed in parallel with the photodiode. The two current sources sum and drive the capacitance seen at node N1, which will be the sum of gate capacitances of inverters 1 and 2. An ideal voltage controlled switch connects N1 to ground. When the switch is closed, node N1 sees a direct path to ground. When the switch is open, the current sources charge the capacitances at N1, producing a voltage ramp at that node. The difference in VM between inverters 1 and 2 produce the time delay between the steps at N2 and N3. Inverters 3 and 4 clean up the output signals from inverters 1 and 2. Your task is to design the four inverters 1–4. To maintain compatibility with the 200MHz system clock, the time delay between voltage steps generated in this stage should be no less than 20ns. The minimum difference between time delays generated by different light intensities should also be 20ns. That is, if at some Ilight the generated delay is 20ns, then at the next Ilight level, the time delay should be no less than 40ns, and so on.High gain inverters 1 and 2 should be sized to achieve the appropriate VM and gate capacitance, chosen to achieve the delay specifications while trying to minimize the total gate area of Stage 1. Your project will be evaluated based on how low gate area you achieve, which should not exceed 400µm2. 2.2 STAGE 2 Stage 2 takes as inputs the time delayed steps from Stage 1, and outputs a single pulse whose width is the time delay between the two Stage 1 steps. A device that can accomplish this is an XOR gate. Show using a truth table why this is true. Your task is to design an XOR gate. The XOR gate should be composed of AND, OR gates, or their complements as well as inverters if needed. 2.3 STAGE 3 The output buffer is a chain of inverters designed to drive 5pF. Your task is to determine how many and what size inverters are necessary to drive 5pF and generate a positive going pulse at VOUT. The inverters should be individually sized to drive the increasing load capacitance seen at the output of each subsequent inverter. Rise and fall times at VOUT should each not exceed 3ns, measured from the 10% to 90% points. The total gate area for stage 2 and 3 should not exceed 600µm2, and as with Stage 1, you should try to achieve as low gate area as you can design. 2.4 SUMMARY OF SPECIFICATIONS Supply VDD = 3V Stage 1 Maximum gate area 400 µm2 Minimum pulse width 20 ns Minimum output step size 20 ns Stage 2&3 Maximum total gate area 600 µm Stage 3 Maximum tr, tf 3 ns Load capacitance 5 pF3 Calculations Before simulating, you should make sufficient calculations to choose appropriate transistor sizes to meet specifications. You should get a good feel for the tradeoffs you will need to make and which performance parameters are affected by your sizing decisions. Be prepared to explain your calculations and tradeoff decisions in your design report. 3.1 MOSFET PARAMETERS The MOSFETS we have available to us in this process have the following properties: 1. Threshold voltages are fixed at VTn = 0.5 [V], VTp = -0.5 [V]. 2. Oxide thicknesses are fixed at tOX = 15 [nm]. 3. Mobility: µn=220 [cm2/Vs] for the NMOS, µp=110 [cm2/Vs] for the PMOS. 4. Junction capacitance (CJ) = 1x10-4 [F/m2] NMOS, 3x10-4 [F/m2] PMOS. 5. Sidewall junction capacitance (CJSW) = 5x10-10 [F/m] (NMOS), 3.5x10-10 [F/m] (PMOS) 6. Built in potential ØB (PB) = 0.95 [V] (NMOS), 0.9 [V] (PMOS) 7. The parameter LAMBDA=67 mV-1 is known for 1.5µm long devices. When using lengths other than 1.5µm, it is necessary to adjust the value of λ. For a MOSFET of length L, the new λ value is (1.5/L)*67 mV-1. This is because λ is proportional to (1/L). For your convenience, we have created sub-circuits which are simply a MOSFET but have the λ value and geometries computed for you. 8. The backgate is tied to GND for N-MOSFETS, and VDD for P-MOSFETS. 3.2 MINIMUM TRANSISTOR SIZES Minimum Size Transistor: Top View A minimum size
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