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MIT 6 012 - Design Problem Circuit

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6.012 - Microelectronic Devices and Circuits Spring 2006 Design Problem Circuit Full schematic Q19Q21Q27Q26Q28Q29vOUT+-BvIN2Q16+ 1.5 V- 1.5 VQ12Q11BvIN1+-+-Q13Q14Q15Q10Q9Q18Q20Q17Q25Q24AQ23Q22Q5CDCABQ6Q7DQ8Q1Q2Q3Q4Bias chains Source-coupled pair gain stage with Lee active load Cascode* differential gain stage with cascode current mirror active load Complementary emitter-follower output stages Push-pull output stage * Common source stage followed by common base stage. 6.012 Design Problem Spring 2006 - Slide 1Circuit drawn with alternative MOSFET symbols:Some find the MOSFET symbols used in this version of the schematic with thearrow on the source, rather than the gate, more intuitive when looking at aschematic. The rest of the foils in this set use the original symbols, so this figure help you adapt those foils if you prefer these alternative symbols. Q19Q21Q27Q26Q28Q29vOUT+-BvIN2Q16+ 1.5 V- 1.5 VQ12Q11BvIN1+-+-Q13Q14Q15Q10Q9Q18Q20Q17Q25Q24AQ23Q22Q5CDCABQ6Q7DQ8Q1Q2Q3Q4Bias chains Source-coupled pair gain stage with Lee active load Cascode* differential gain stage with cascode current mirror active load Complementary emitter-follower output stages Push-pull output stage 6.012 Design Problem •Common source stage followedby common base stage. Spring 2006 - Slide 2Conceptual schematic: full circuit Q21Q26Q28Q29vOUT+-vIN2+ 1.5 V- 1.5 VvIN1+-+-Q13Q14Q25Active Load (Current mirror cascode load)IBIAS1IBIAS2IBIAS3Active load (Lee load)Q19Q16Q18Q17CSource-coupled pair Source-coupled pair Complementary Push-pull gain stage with stage followed by emitter-follower output Lee active load common gate stage output stages stage with cascode current mirror active load 6.012 Design Problem Spring 2006 - Slide 3Conceptual schematic: difference-mode inputs +-Q13Q26Q28roQ24gCL,diffgLL,diff Q17vod+-100!vid/2 Q19Common Source Common Gate Emitter Follower Emitter Follower Common Source Avd = vod/vid 6.012 Design Problem Spring 2006 - Slide 4gLL,comvic+-Q13Q26Q28roQ242roQ15gCL,com Q17voc+-100! Q19Conceptual schematic: common-mode inputs Common Source Common Gate Emitter Follower Emitter Follower Source Degeneration (parallel feedback) Avc = voc/vic 6.012 Design Problem Spring 2006 - Slide 5+ 1.5 VABQ1Q2Q3Q4- 1.5 VABQ1Q4- 1.5 VRREF1+ 1.5 V≈ Q5CQ6Q7DQ8- 1.5 V+ 1.5 V- 1.5 V+ 1.5 VRREF2RREF3RREF3RREF2DCLeft to right through the design problem circuit:1. Biasing: the bias chains Points to ponder:- What is the drain current of a minimum size n-channel MOSFET when (VGS-VT) = (VGS-VT)min? What is it for a minimally biased p-channel MOSFET? - How can Q1 and Q4 both be at this minimum bias point? 6.012 Design Problem Spring 2006 - Slide 6Left to right through the design problem circuit:1. Biasing: looking at how each of the four stages is biased Q21Q26Q28Q29vOUT+-vIN2+ 1.5 V- 1.5 VQ12Q11vIN1+-+-Q13Q14Q10Q9Q20Q25Q23Q22DQ19Q16Q18Q17CIBIAS1IBIAS2IBIAS3Stage 1: BiasedStage 2: BiasedStage 3: BiasedStage 4:by the currentby Q9, Q10, Q11, by IBIAS2 and Biased bysource, IBIAS1 and Q12. IBIAS3. Q25and Q26. Point to ponder:6.012 Design Problem - Stages 2 and 4 are biased by the preceding stages. Spring 2006 - Slide 7Left to right through the design problem circuit:1. Biasing: power dissipation A constraint on the bias currents is the total power dissipationspecification of 7.5 mW. This means that the total bias currentmust be less that 2.5 mA (i.e, 3 V x 2.5 mA = 7.5 mW). Q19Q21Q27Q26Q28Q29vOUT+-BvIN2Q16+ 1.5 V- 1.5 VQ12Q11BvIN1+-+-Q13Q14Q15Q10Q9Q18Q20Q17Q25Q24AQ23Q22Q5CDCABQ6Q7DQ8Q1Q2Q3Q4IA IB IC ID IG IHIFIE ! IA+ IB+ IC+ ID+ IE+ IF+ IG+ IH" 2.5 mA! PQ= IA+ IB+ IC+ ID+ IE+ IF+ IG+ IH( )" 3 Volts6.012 Design Problem Spring 2006 - Slide 8Left to right through the design problem circuit:2. First gain stage: gain of source-coupled pair with Lee load A Lee Load is an active load that looks different in common anddifference mode. A full analysis can be found in the handout"Two Active Loads" posted on Stellar. vIN2Q12Q11BvIN1+-+-Q13Q14Q15Q10Q9vOUT1+-vOUT2+-+ 1.5 V- 1.5 V+-vgs13gm13vgs13go132gm9+-vic+-voc2r015gm13vidgo132go9+-vid+-vodDifference mode: Common mode: 6.012 Design Problem Spring 2006 - Slide 9Left to right through the design problem circuit:2. First gain stage: gain of source-coupled pair with Lee load Difference mode: Common mode: gm13vidgo132go9+-vid+-vod+-vgs13gm13vgs13go132gm9+-vic+-voc2r015! vod="gm13g013+ 2g09vid =2ID13VGS13"VTn( )ID13VA13+ 2ID132VA9vid=2VA 9VA13VA 9+ VA13# $ % & ' ( VGS13"VTn( )vid=2VA,eff 9,13VGS13"VTn( )vid! voc"#g0154gm9vic=VGS9# VTp( )2VA15vicCombined: ! vout1="gm13go13+ 2go9#vin1" vin2( )2"g0154gm9#vin1+ vin2( )2="VA.eff 9,13VGS13" VTn( )# vin1" vin2( )"VGS13" VTn( )2VA15#vin1+ vin2( )2vout2=gm13go13+ 2go9#vin1" vin2( )2"g0154gm9#vin1+ vin2( )2=VA.eff 9,13VGS13" VTn( )# vin1" vin2( )"VGS13" VTn( )2VA15#vin1+ vin2( )2Points to ponder:- The outputs go to the gates of other MOSFET, so they do not load this stage. What does this about getting the maximum difference mode out of this stage? - How can Q9 through Q15 all be biased at their minimum bias point? 6.012 Design Problem Spring 2006 - Slide 10Left to right through the design problem circuit:2. First gain stage, cont: common-mode input range Point to ponder:- What is vDS and what is vGD at the boundary between the saturation and linear regions? --vcdownvCupQ13, Q14 forcedout ofsaturationif vC too highvCdownvCup++--vGS stays constantQ15 forced outof saturationif vc too lowvGSvGS++vSG stays constant-+Q12Q11BQ13Q14Q15Q10Q9+ 1.5 V- 1.5 V6.012 Design Problem Spring 2006 - Slide 11Left to right through the design problem circuit:3. Second gain stage: source-coupled cascode, current mirror load Comments/Observations:- This stage is essentially a normalsource-coupled pair with a currentmirror load, but there are differences.. - The first difference is that two drivertransistors are cascode pairs. The stagethus has two sub-stages, the first being asource-coupled pair which is loaded bythe second, which is a common-gatepair. The combination of a commonsource stage followed by a common gatestage is called a "cascode. - The second difference is that thecurrent mirror load is also cascoded. - The third difference is that the stage isnot biased with a current mirror, but isinstead biased by the first gain stage. Q19Q21Q16Q18Q20Q17Q23Q220.75 V-0.75 VvOUT+-vIN2+-vIN1+-- 1.5 V+ 1.5 Vrin3Point to ponder:- Notice that output of the stage is loaded by the input resistance of the third stage.In the first


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MIT 6 012 - Design Problem Circuit

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