_____________________________________________________________ 6.012 Microelectronic Devices and Circuits Spring 2007 March 14, 2007 Quiz #1 Problem #points NAME___________________________________ 1___________ RECITATION TIME___________________________ 2___________ 3___________ Total______________ General guidelines (please read carefully before starting): • Make sure to write your name on the space provided above. • Open book: you can use any material you wish. But no computers. • All answers should be given in the space provided. Please do not turn in any extra material. • You have 120 minutes to complete the quiz. • Make reasonable approximations and state them, i.e. low-level injection, extrinsic semiconductor, quasi-neutrality, etc. • Partial credit will be given for setting up problems without calculations. NO credit will be given for answers without reasons. • Use the symbols utilized in class for the various physical parameters, i.e. Na, τ, ε, etc. • Pay attention to problems in which numerical answers are expected. An algebraic answer will not accrue full points. Every numerical answer must have the proper units next to it. Points will be subtracted for answers without units or with wrong units. In situations with a defined axis, the sign of the result is also part of the answer. Unless otherwise stated, use: q = 1.6 X 10-19 C kT/q = 25 mV at room temperature ni = 1010 cm -3 for silicon at room temperature εsi = 10-12 F/cm εox = 3.45X10-13 F/cm 11um1um1. (30 points) The following is a serpentine IC resistor made by ion-implantation of Phosphorus into p-type Si. The repeating stripes have length of 10 µm, and width of 1 µm, and the connecting regions are 1x1µm. The dimensions are shown below. The Phosphorus dose implanted per unit area equals Q=1013 cm -2, and the thickness after post-annealing is t=0.1µm. You may ignore the contact potential effect and assume uniform doping. Please use Figure 2 below to derive mobility. Figure 1: TOP VIEW 1 µm V+ 10 µm Figure 2: 1400 1200 1000 800 600 400 200 0 holes electrons mobility (cm2 /Vs) 1013 1014 1015 1016 1017 1018 1019 1020 Nd + Na total dopant concentration (cm−3) 2(a) Compute the doping concentration in the resistor, assuming that the Phosphorus concentration is constant down to a depth of 0.1 µm. Indicate the majority and minority carriers and calculate their concentration in thermal equilibrium at room temperature. (b) Compute the total resistance of the structure. 3(c) If the voltage is 1V, calculate the electric field inside one of the 10 µm x1µm stripes. (d) In reality, the electron velocity will saturate when the electric field inside the semiconductor reaches a certain value. The saturation velocity of the majority carrier is 107 cm/s. Calculate: a. The voltage when this happens, b. The maximum drift current that can flow, assuming that the carriers are drifting at the saturation velocity. 42. (35 points) Consider the n+ p diode shown below in thermal equilibrium. The n+ doping is high enough such that you can assume that φ += 0.55V , and that no potential drop occurs on n the n+ side of the junction. Assume that the p -Si region between x =−L and x = 0 is very lightly doped (i.e. Na < 1015 cm −3 ). n + Si p -Si p Si Na=1017 cm -3 Region Region (1) (2) x −L 0 −5L = 0.2µm = 2x10 cm (a) Calculate the built-in potential across the structure. 5(b) Sketch the electric field vs x in the structure assuming you can ignore the depletion charge in region (1). You do not need to calculate numerical values, but label the curves in the various regions with the dependence on x (e.g. linear, quadratic, etc.). E x 0−L (c) Calculate the distance the depletion region extends into region (2) (i.e. beyond x = 0 ). (Hint: treat region (1) as a dielectric without charge) 6(d) Calculate the potential drop across region (1), ∆V1 and the potential drop across region (2), ∆V2, and sketch φ(x) vs. x on the axes below. Label all the relevant potential drops on the sketch. φ x −L 0 (e) Calculate the depletion capacitance of the structure at V = 0V , in units of F/cm2. 73. (35 points) You are given an MOS capacitor with a p+ polysilicon gate. The capacitor has: Area=10-4 cm 2 Na=1017 cm -3 and the C-V curve given below. C 34.5pF VFB VT VG (a) Calculate the oxide thickness. Note: capacitance is given in pF not pF/cm2. (b) Calculate the electric field in the oxide when the gate voltage equals VT. 8(c) Calculate VFB. (d) Given a 10µA current source is used to discharge the capacitor from VT to VFB, calculate how long it will take. Recall 10µA = 10µC / sec . VG starts at VT10µA G VG ends at VFB V− + ↓ 9(e) We replace the current source with an NMOS transistor W / L = 20 and VGS − VT = 0.1V . Calculate the mobility of the channel electrons such that the transistor drain current is 10µA . Assume the oxide thickness is the same as in part (a) and VSB = 0V and λ= 0 . V10µA VG − +↓ −+− + G S VSB (f) If the transistor has a backgate voltage of VSB = 2V , calculate the new gate-to-source voltage, VGS , to produce the same current, 10µA . 10MIT OpenCourseWarehttp://ocw.mit.edu 6.012 Microelectronic Devices and Circuits Spring 2009 For information about citing these materials or our Terms of Use, visit:
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