Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models Outline • Low-frequency small-signal equivalent circuit model • High-frequency small-signal equivalent circuit model Reading Assignment: Howe and Sodini; Chapter 4, Sections 4.5-4.6 6.012 Spring 2009 Lecture 10 1Large Signal Model for NMOS Transistor • Cut-off • Linear / Triode: • Saturation Regimes of operation: Effect of back bias I D = 0 I D = W L μnCox VGS VDS 2 VT • VDS ID = IDsat = W 2L μnCox VGS VT[ ]2 • 1 + VDS[ ] VT(VBS ) = VTo + 2p VBS 2p[ ] VDS ID VGS VGS=VT VDSsat=VGS-VT 0 0 linear saturation cutoff VGS VBS VDS �ID 6.012 Spring 2009 Lecture 10 2Small-signal device modeling • Small-signal is small – response of non-linear components becomes linear • Since response is linear, lots of linear circuit techniques such as superposition can be used to determine the circuit response. • Notation: iD = ID + id ---Total = DC + Small Signal Key Points: In many applications, we are only interested in the response of the device to a sm all-signal applied on top of a bias. VGS VBS VDS �ID+id vgs vbs vds + -++ --6.012 Spring 2009 Lecture 10 3Mathematically: With id linear on small-signal drives: iD(VGS, VDS, VBS; vgs, vds , vbs ) ID VGS, VDS, VBS( ) + id (vgs, vds, vbs ) id = gmvgs + govds + gmbvbs Define: gm transconductance [S] go output or drain conductance [S] gmb backgate transconductance [S] Approach to computing gm, go, and gmb. gm iD vGS Q go iD vDS Q gmb iD vBS Q Q [vGS = VGS, vDS = VDS, vBS = VBS] 6.012 Spring 2009 Lecture 10 4Transconductance In saturation regime: iD = W 2L μnCox vGS VT[ ]2 • 1 + VDS[ ] Then (neglecting channel length modulation) the transconductance is: gm = iD vGS Q W L μnCox VGS VT( ) Rewrite in terms of ID: gm = 2 W L μnCox ID ID gm 0 0 saturation 6.012 Spring 2009 Lecture 10 5Transconductance (contd.) Equivalent circuit model representation of gm: G S D B + -vgs gmvgs id 1 100 200 300 400 iD� (μA) vDS (V) VGS + vgs Q ID + id VDS 5432 ID id id = gmvgs VGS 6.012 Spring 2009 Lecture 10 6Output conductance In saturation regime: W 2iD = 2L μnCox [vGS VT ]•[1 + vDS ] Then: W 2 iDgo = = μnCox (VGS VT )• ID2L vDS Q Output resistance is the inverse of output conductance: 1 1 r = = o go ID Remember also: 1 L Hence: r Lo 6.012 Spring 2009 Lecture 10 7Output conductance (contd.) Equivalent circuit model representation of go: G S D B + -vgs ro id iD� (μA) ID + id vds VDS VDS + vds VDS (V) ID id id = govds VGS, VBS 1 100 200 300 400 Q 5432 6.012 Spring 2009 Lecture 10 8Backgate transconductance In saturation regime (neglect channel length modulation): iD W 2L μnCox vGS VT[ ] 2 Then: gmb = iD vBS Q = W L μnCox VGS VT( ) • VT vBS Q Since: Then : VT vBS Q = 2 2p VBS Hence: VT(vBS ) = VTo + 2p vBS 2p[ ] gmb = gm 2 2p VBS 6.012 Spring 2009 Lecture 10 9Backgate transconductance (contd.) Equivalent circuit representation of gmb: G S D B + -vgs gmbvbs + vbs -id iD� (μA) ID + id VDS VDS (V) ID id id = gmbvbs VGS, VBS + vbs VGS, VBS 1 100 200 300 400 Q 5432 6.012 Spring 2009 Lecture 10 106.012 Spring 2009 Lecture 10 Metal interconnectto gateMetal interconnect to bulkn+ polysilicon gatexy0p-typeQN(y)Xd(y)+-+- VDS VGS VBS = 0n+ source n+ drainFigure by MIT OpenCourseWare.6High-frequency small-signal equivalent circuit model Need to add capacitances. In saturation: fringe electric field lines \ gate......................................................source ............................................................................................................................................................................................................................................................................................................................................................... , n+ =',b 4k ~N(%s) 4k1%depletion] overlapL-overlap LD region I Cgs = channel charge + overlap capacitance, C,, Cg, =overlap capacitance, C,, CSb= sourcejunction depletion capacitance (+sidewall) C, =drain junction depletion capacitance (+sidewall) ONLY Channel Charge Capacitance is intrinsic to device operation. All others are parasitic. 6.012Spring 2009 Lecture 10Inversion layer charge in saturation qN (vGS ) = WQN (y)dy 0 L = W QN (vC )• dy dvC0 vGS VT • dvC Note that qN is total inversion charge in the channel & vC(y) is the channel voltage. But: dvC dy = iD W μnQN (vC ) Then: qN (vGS ) = W 2μn iD • QN (vC )[ ]2 0 VGS VT • dvC Remember: QN (vC ) = Cox vGS vC (y) VT[ ] Then: qN (vGS ) = W 2 μnC2 ox iD • vGS vC (y) VT[ ]2 0 vGS VT • dvC 6.012 Spring 2009 Lecture 10 13Inversion layer charge in saturation (contd.) qN (vGS ) = 2 3 WLCox vGS VT( ) Gate charge: qG (vGS ) = qN (vGS ) QB,max Intrinsic gate-to-source capacitance: Cgs, i = dqG dvGS = 2 3 WLCox Must add overlap capacitance: Gate-to-drain capacitance — only overlap capacitance: Cgd = WCov Cgs = 2 3 WLCox + WCov Do integral, substitute iD in saturation and get: 6.012 Spring 2009 Lecture 10 14ther capacitances ............................................................ Source-to-Bulk capacitance: csb = WLdvf cj +(2~di&f+w)cjsw where C :Bottom Wall at Vm (F 1em2) Side Wall at VSB(F1cm)Cjsw Drain-to-Bulk capacitance: Cdb =WLdiffj + (2~dij-f+w)cjsw where Cj :Bottom Wall at VDB(FI cm2) Side Wall at VDB(F1cm)Cjsw Gate-to-Bulk capacitance: 6.012Spring 2009 Lecture 10 .WWhat did we learn today? Summary of Key Concepts gm W L ID ro L ID Cgs WLCox High-frequency small-signal equivalent circuit model of MOSFET In saturation: G S D B + -vgs Cgs Cgb Cgd Cdb Csb gmvgs gmbvbs ro + vbs -id 6.012 Spring 2009 Lecture 10 16MIT OpenCourseWarehttp://ocw.mit.edu 6.012 Microelectronic Devices and Circuits Spring 2009 For information about citing these materials or our Terms of Use, visit:
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