6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 12-1Lecture 12 - Digital Circuits (I)The inverterOctober 20, 2005Contents:1. Introduction to digital electronics: the inverter2. NMOS inverter with resistor pull upReading assignment:Howe and Sodini, Ch. 5, §§5.1-5.3.26.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 12-2Key questions• What are the key figures of merit of logic circuits?• How can one make a simple inverter using a singleMOSFET?6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 12-31. Introduction to digital electronics: the in-verterIn digital electronics, digitally-encoded information is rep-resented by means of two distinct voltage ranges:Vlogic 1logic 0undefined regionVOLVMAXVMINVOH• logic 0: VMIN≤ V ≤ VOL• logic 1: VOH≤ V ≤ VMAX• undefined logic value: VOL≤ V ≤ VOH.Logic operations are performed using logic gates.Simplest logic operation of all: inversion ⇒ inverter6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 12-42 Ideal inverter:INOUT=ININOUT0110Circuit representation and ideal transfer function:v+++--VINVOUTVOUTVINV+V+V+2VOUT=VINV+2VM=00Define switching point or logic threshold :VM≡ input voltage for which VOUT= VIN-for 0 ≤ VIN≤ VM⇒ VOUT= V+-for VM≤ VIN≤ V+⇒ VOUT=06.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 12-5Key property of ideal inverter: signal regenerationv+++--VINVOUTVOUTVINV+V+V+2VOUT=VINV+2VM=00Ideal inverter returns well defined logical outputs (0 orV+) even in the presence of considerable noise in VIN(from voltage spikes, crosstalk, etc.)V+VMVIN0V+VMVOUTVOUT0V+VMVIN0V+VM0VOUTV+VMVIN0V+VM0pulse edge sharpeningnoise suppressionlogic level restoration6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 12-62 ”Real” inverter:VOUTVINV+00slope=-1VOHVOLVMINVMAXlogic 1logic 0undefined region|Av|>1V+v+++--VINVOUTIn a real inverter, valid logic levels defined as follows:• logic 0:VMIN≡ output voltage when VIN= V+VOL≡ smallest output voltage where slope=-1• logic 1:VOH≡ largest output voltage where slope=-1VMAX≡ output voltage when VIN=06.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 12-7Two other important voltages:logic 1logic 0undefined region|Av|>1edges sharpened|Av|<1 noise suppressed|Av|<1 noise suppressedVOUTVINV+00slope=-1VOHVILVIHVOLVMINVMAXrange of input values thatproduce acceptable logic 0range of input values thatproduce acceptable logic 1VIL≡ smallest input voltage where slope=-1VIH≡ highest input voltage where slope=-1To have signal regeneration:range of input values that pro duce acceptable logic output> range of valid logic valuesKey to signal regeneration in inverter: high voltage gain6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 12-8Quantify signal regeneration through noise margins.Consider chain of two inverters:noiseMNinverter Moutputinverter NinputVOHVMAXVMINVMINVMAXVOUTVINNMHNMLVOLVIHVILDefine noise margins:NMH= VOH− VIHnoise margin highNML= VIL− VOLnoise margin lowWhen signal is within noise margins:• logic 1 output from first inverter interpreted as logic1 input by second inverter• logic 0 output from first inverter interpreted as logic0 input by second inverter6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 12-9Simplifications for hand calculationsHard to compute Av= −1 points in transfer function.Approximate calculation:VOUTVIHVILVMVMVINV+00VOL=VMINVOH=VMAXVOUT=VINslope= Av(VM)• Assume VOL' VMINand VOH' VMAX• Trace tangent of transfer function at VM(slope=small signal voltage gain at VM)• VIL' intersection of tangent with VOUT= VMAX• VIH' intersection of tangent with VOUT= VMIN• to enhance noise margin: |Av(VM)|↑6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 12-10VOUTVIHVILVMVMVINV+00VOL=VMINVOH=VMAXVOUT=VINslope= Av(VM)|Av(VM)|'VMAX− VMVM− VIL⇒ VIL' VM−VMAX− VM|Av(VM)||Av(VM)|'VM− VMINVIH− VM⇒ VIH' VM(1 +1|Av(VM)|) −VMIN|Av(VM)|Then:NML= VIL−VOL' (VMAX−VMIN)−(VMAX−VM)(1+1|Av(VM)|)NMH= VOH−VIH' (VMAX−VMIN)−(VM−VMIN)(1+1|Av(VM)|)If |Av(VM)|→∞:NML→ VM− VMINNMH→ VMAX− VM6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 12-112 Transient characteristicsLook at inverter switching in the time domain:VOL90%50%10%tPHLtPLHVOHtRtCYCLE50%90%10%0tVINVOUT0ttRtFVOHVOLtFINOUTtR≡ rise time between 10% and 90% of total swingtF≡ fall time between 90% and 10% of total swingtPHL≡ propagation delay from high-to-low between50% pointstPLH≡ propagation delay from low-to-high between50% pointsPropagation delay: tP=12(tPHL+ tPLH)6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 12-12Propagatio n delay: simplification for hand calculations• Input wavefunction = ideal square wave• Propagation delay times = delay times to 50% pointVOHVOHVOLVINVOUTtPHLtPLHVOHVOL50%tttCYCLEtCYCLE• Hand calculations only approximate• SPICE essential for accurate delay analysis6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 12-132. NMOS inverter with resistor pull upVINVOUTV+=VDDIRIDCLRload capacitance(from followingstages)Features:• VBS= 0 (typically not shown)• CLsummarizes capacitive loading of following stages(other logic gates, interconnect lines)Basic operation:• if VIN<VT, MOSFET OFF ⇒ VOUT= VDD• if VIN>VT, MOSFET ON ⇒ VOUTsmall (value setby resistor/nMOS divider)6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 12-14VINVRVOUTVDDIRIDR+-Transfer function obtained by solving:IR= IDCan solve graphically: I-V characteristics of pull-up re-sistor on IDvs. VOUTtransistor characteristics:IR=IDVR=VDD-VOUT0 0001/RIR=IDVR-VDD=-VOUT1/R-VDDIR=IDVOUT1/RVDDVDDRVDDR6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 12-15Overlap I-V characteristics of resistor pull-up on I-V char-acteristics of transistor:VDS=VOUTVGS=VDDVGS=VINVGS=VT00IR=IDVDDVDDRload lineTransfer function:VOUT=VDSVIN=VGS00VDDVTVDD6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 12-16Logic levels:VOUT=VDSVOUT=VINVIN=VGS00VDDVTVMVMVMAX=VDDVMINFor VMAX, transistor is cut-off, ID=0:VMAX= VDDFor VMIN, transistor is in linear regime; solve:ID=WLµnCox(VDD−VMIN2−VT)VMIN= IR=VDD− VMINRFor VM, transistor is in saturation; solve:ID=W2LµnCox(VM− VT)2= IR=VDD− VMRWill continue next lecture with analysis of noise marginand dynamics...6.012 - Microelectronic
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