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MIT 6 012 - Study Guide

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6.012 Microelectronics Devices and Circuits Fall 2005 1 Cadence Tutorial (Part Two) By Kerwin Johnson Version: 10/24/05 (based on 6.776 setup by Mike Perrott) Table of Contents Introduction.......................................................... .............................2 Upgrade the Device Models...............................................................3 Update the Schematic for the Transient Simulation...........................6 Transient Simulation.........................................................................9 Analysis...........................................................................................11 Plot the Transient Output ............................................................11 Calculate Delays, Rise Times and Power Consumption.................12 Parametric Simulation.....................................................................156.012 Microelectronics Devices and Circuits Fall 2005 2 Introduction In this second tutorial we will build on what we learned in the first tutorial. We will learn more sophisticated modeling techniques and more powerful simulation skills. We will use them to answer the question, “For a given load capacitor and a maximum required rise and fall time what is the minimum power required to meet these specs?” For this we will find useful models that automatically include the increase in source and drain depletion capacitance with increases in the device size. So we will use a parameterized subcircuit around the mos1 model that we created in the first tutorial. In order to find the rise time, the fall time and the power per cycle we will run a transient simulation. In order to answer the optimization question, we will use a parametric simulation as an insightful way to pursue the answer.6.012 Microelectronics Devices and Circuits Fall 2005 3 Upgrade the Device Models We remember from the first tutorial that we didn't include the variation of lambda with length in the device model. Also the variation of the source and drain impedance is controlled by setting it per instance in the schematic. This is tedious. We will change the models. We will add two new techniques to our modeling repertoire which we have seen in netlists previously. The first is that we will create our entire model within a subckt statement the same as our inverter was when we looked at the netlist. Secondly, we will use parameter statements to re-calculate the source and drain values for each instantiated mos device. Again we used this technique to vary the input DC source in the first tutorial. We will also use one piece of spectre magic, called the inline statement. The inline statement precedes the word subckt and it makes the instantiated element within the subckt with the same name look like the entire subckt for the purposes of probing. All this means is that when we are plotting data, the subckt containing a pmos looks like a pmos model directly for the purposes of plotting. Edit your mos6012.scs file and add the following. You can leave the models from the first tutorial intact because we are changing the model name from nmos6012 to nmos6012p for parameterized. // Created by: Kerwin Johnson Sept 2005. simulator lang=spectre insensitive=yes inline subckt nmos6012p (d g s b) parameters w=3e-6 l=1.5e-6 as=1.35e-11 + ad=1.35e-11 ps=1.2e-5 pd=1.2e-5 + nrs=1.5 nrd=1.5 lds=4.5e-6 ldd=4.5e-6 model nmos6012i mos1 + type = n + l = l + w = w + vto = 0.75 + kp = 100e-6 + lambda = 7e-2 * (1.5e-6 / l) + phi = 0.7 + gamma=0.6 + tox = 1.5e-8 + cj = 1e-4 + cjsw = 5e-10 + pb = 0.94 6.012 Microelectronics Devices and Circuits Fall 2005 + lds = lds + ldd = ldd + as = max( lds * w, as) + ad = max( ldd * w, ad) + ps = max(w + 2 * lds, ps) + pd = max(w + 2 * ldd, pd) nmos6012p (d g s b) nmos6012i ends inline subckt pmos6012p (d g s b) parameters w=6e-6 l=1.5e-6 as=2.7e-11 + ad=2.7e-11 ps=1.5e-5 pd=1.5e-5 + nrs=1.5 nrd=1.5 lds=4.5e-6 ldd=4.5e-6 model pmos6012i mos1 + type = p + l = l + w = w + vto = -0.75 + kp = 50e-6 + lambda = 7e-2 * (1.5e-6 / l) + phi = 0.7 + gamma=0.6 + tox = 1.5e-8 + cj = 3e-4 + cjsw = 3.5e-10 + pb = 0.9 + lds = lds + ldd = ldd + as = max( lds * w, as) + ad = max( ldd * w, ad) + ps = max(w + 2 * lds, ps) + pd = max(w + 2 * ldd, pd) pmos6012p (d g s b) pmos6012i6.012 Microelectronics Devices and Circuits Fall 2005 5 ends If you have changed the name of the model file, then you need to change the location in ADE as well.6.012 Microelectronics Devices and Circuits Fall 2005 6 Update the Schematic for the Transient Simulation We want to run a transient simulation to measure rise time, fall time and power consumed by the inverter driving a load capacitance of 500f. We will start with the previous test_inverter schematic and change what we need as we go along. To begin we need to change the input from a dc source into a square wave, and we need to change the models that the mos devices are referencing to our new models. Do the following. 1. Open the library browser CIW->Tools->Library Manager and open the test_inverter schematic. 2. Change the models on the FETs inside the inverter. Descent into the inverter (E), (q)uery the pmos and change its model to pmos6012p. Change the nmos model to nmos6012p. Check and Save (X) and then ascend (Ctrl-e) to the test_inverter schematic. 3. Change the input source to a square wave. (q)uery the vdc used for vin. Change the cell name to vpulse. Set voltage 1 = 0, voltage 2 = vdc, rise time = trise, period = tperiod and pulse width = tperiod/2-trise. When you are done compare it with the picture below and then click OK.7 6.012 Microelectronics Devices and Circuits Fall 2005 Courtesy of Cadence Design Systems, Inc. Used with permission.8 6.012 Microelectronics Devices and Circuits Fall 2005 4. Change the load capacitance to 500f. 5. Check and Save (X).6.012 Microelectronics Devices and Circuits Fall 2005 9 Transient Simulation. In this section we will run ADE and configure a transient simulation to run. In order to do this we will load the previous dc simulation that we ran and add a transient simulation to it. If you didn't save the previous dc simulation, then follow the instructions in the previous tutorial to setup the dc simulation. 1. Start ADE by Tools->Analog Environment. 2. Load your final state from the first tutorial, with Session ->Load State. Pick the name that you saved it under and click OK. 3. Add the design variables for the vpulse


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MIT 6 012 - Study Guide

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