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MIT 6 012 - Digital Circuits

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Lecture 13 Digital Circuits (III) CMOS CIRCUITS Outline • CMOS Inverter: Propagation Delay • CMOS Inverter: Power Dissipation • CMOS: Static Logic Gates Reading Assignment: Howe and Sodini; Chapter 5, Sections 5.4 & 5.5 16.012 Spring 2009 Lecture 131. Complementary MOS (CMOS) Inverter • VIN = 0 ⇒ VOUT = VDD – VGSn = 0 ( < VTn ) ⇒ NMOS OFF – VSGp = VDD ( > - VTp ) ⇒ PMOS ON • VIN = VDD ⇒ VOUT = 0 – VGSn = VDD ( > VTn ) ⇒ NMOS ON – VSGp = 0 ( < - VTp ) ⇒ PMOS OFF Circuit schematic: Basic Operation: VIN VOUT VDD CL 26.012 Spring 2009 Lecture 13 No power consumption while idle in any logic state!2. CMOS inverter: Propagation delay Inverter propagation delay: time delay between input and output signals; figure of merit of logic speed. Typical propagation delays: < 100 ps. � C omplex logic system has 10-50 propagation delays per clock cycle. Estimation of t p : use square-wave at input Average propagation delay: t p = 1 2 tPHL + tPLH( ) VDD VDD 0 VIN VOUT tPHL tPLH 0 50% t t tCYCLE tCYCLE 36.012 Spring 2009 Lecture 13CMOS inverter: Propagation delay high-to-low During early phases of discharge, NMOS is saturated and PMOS is cut-off. Time to discharge half of charge stored in CL:. � t pHL ≈ 1 2 charge on CL @t = 0 − NMOS discharge current VIN:- LO HI VOUT:- HI LO VDD CL VIN=0 VOUT=VDD VDD t=0-t=0+ CL VIN=VDD VOUT=VDD VDD CL t->infty VIN=VDD VOUT=0 VDD CL 46.012 Spring 2009 Lecture 13CMOS inverter: Propagation delay high-to-low (contd.) Then: tPHL ≈ CLVDD W n L n µn C ox VDD − VTn( )2 QL t = 0−( )= CLVDD I Dn = W n 2L n µn C ox VDD − VTn( )2 Charge in CL at t=0-: Discharge Current (NMOS in saturation): Graphical Interpretation ID 2 t = tPHL t = 0+ t = 0− VIN = 0V VIN = VOH tPHL t 2 (a) (b) VOUTVOHVOH VOUT VOH VOH 0 0 0 0 56.012 Spring 2009 Lecture 13CMOS inverter: Propagation delay low-to-high During early phases of discharge, PMOS is saturated and NMOS is cut-off. Time to charge to half of final charge on CL:. � tPLH ≈ 1 2 charge on CL @t = ∞ PMOS charge current VIN:-HI LO VOUT:-LO HI VDD CL VIN=VDD VOUT=0 VDD t=0-t=0+ CL VIN=0 VOUT=0 VDD CL t->infty VIN=0 VOUT=VDD VDD CL 66.012 Spring 2009 Lecture 13CMOS inverter: Propagation delay high-to-low (contd.) Charge in CL at t=∞ : QL(t = ∞)= CLVDD Charge Current (PMOS in saturation): p− IDp = W µpCox (VDD + VTp )2 2L p Then: tPLH ≈ W CLVDD 2 p µpCox (VDD + VTp )L p Key dependencies of propagation delay: • VDD ↑ ⇒ tp ↓ – Reason: VDD ↑ ⇒ Q(CL ) ↑, but ID goes as square↑ – Trade-off: VDD ↑ ⇒ more power consumed. • L ↓ ⇒ t ↓ p – Reason: L ↓ ⇒ I ↑D – Trade-off: manufacturing cost! 76.012 Spring 2009 Lecture 13Components of load capacitance CL: • Following logic gates: must add capacitance of each gate of every transistor the output is connected to. • Interconnect wires that connects output to input of following logic gates • Own drain-to-body capacitances CL = CG + Cwire + CDBn + CDBp VDD VDD 1 2 3 W L W L p1 n1 p2 VDD n2 W L W L VV ININ V+ DD VC OUTL p3 − W L W L n3 (a) (b) 86.012 Spring 2009 Lecture 13Gate Capacitance of Next Stage • Estimation of the input capacitance: • n- and p-channel transistors in the next stage switch from triode through saturation to cutoff during a high-low or low-high transition • Requires nonlinear charge storage elements to accurately model • Hand Calculation use a rough estimate for an inverter Cin = Cox (WL)p + Cox (WL)n CG for example circuit CG = Cox (WL)p2 + Cox (WL)n2 + Cox (WL) p3 + Cox (WL)n3 96.012 Spring 2009 Lecture 13Interconnect Capacitance "Wires" consist the inverter to the of metal lines connecti input of the next stage ng the output of ,metal interconnect ...................... 0.6pm deposited oxide 0.5 pm thermal oxide ,+/-I \ Y p (grounded) I \gate oxide The p+ layer (i.e., heavily doped with acceptors) under the thick thermal oxide (500 nm = 0.5 pm) and deposited oxide (600 nm = 0.6 pm) depletes only slightly when positive voltages appear on the metal line, so the capacitance is approximately the oxide capacitance: where the oxide thickness = 500 nm + 600 nm = 1.1 pm. ( For large digital systems, the parasitic wiring capacitance can dominate the load capacitance 6.012 Spring 2009(Parasitic Capacitance-Drain/BuIDepletion k\ A A W 3 6.012 Spring 2009Calculation of Parasitic Drain/Bulk Junction Depletion Capacitance • Depletion qJ(vD) is non-linear --> take the worst case and use the zero-bias capacitance Cjo as a linear charge-storage element during the transient. • “Bottom” of depletion regions of the inverter’s drain diffusions contribute a depletion capacitance: CJBOT = CJn(WnLdiffn) + CJp(WpLdiffp) Where: CJn and CJp are the zero-bias bottom capacitance (fF/µm2) for the n-channel and p-channel MOSFET drain-bulk junction, respectively. Typical numbers: CJn and CJp are about 0.2 fF/µm2 • “Sidewall” of depletion regions of the inverter’s drain diffusions make an additional contribution: CJSW = (Wn + 2Ldiffn)CJSWn + (Wp + 2Ldiffp)CJSWp Where: CJSWn and CJSWp are the zero-bias sidewall capacitance (F/µm) for the n-channel and p-channel MOSFET drain-bulk junction, respectively. Typical numbers: CJSWn and CJSWp are about 0.5 fF/µm The sum of CJBOT and CJSW is the total depletion capacitance, CDB 12 6.012 Spring 2009 Lecture 13Power Dissipation • Energy from power supply needed to charge up the capacitor: Echarg e =∫ VDDi(t)dt = VDDQ = VDD 2CL • Energy stored in capacitor: 2Estore = 1/ 2CLVDD • Energy lost in p-channel MOSFET during charging: Ediss = Echarge − Estore = 1/ 2CLVDD 2 •During discharge the n-channel MOSFET dissipates an identical amount of energy. •If the charge/discharge cycle is repeated f times/second, where f is the clock frequency, the dynamic power dissipation is: 2P = 2Ediss * f = CLVDD f In practice many gates do not change state every clock cycle which lowers the power dissipation. 13 6.012 Spring 2009 Lecture 13CMOS Static Logic Gates VOUT VDD VDD BA M1 M3 M4 M2 M1 M2 M3 M4 A A B A B (a) (b) B + _ VOUT + _ 14 6.012 Spring 2009 Lecture 13CMOS NAND Gate I-V Characteristics of n-channel devices -(as VM 0) @ Effective length of two n-channel devices is 2L, keff=kl/2=162/2 Recall k,=WILpnCOX @Effectivewidth of two p-channel devices is 2W, BUT worst case only one device is on kpeff=kp3 =kp4 6.012 Spring 2009Calculation of static and transient performance for NAND Gate • kpeff =


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MIT 6 012 - Digital Circuits

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