Lecture 11 Digital Circuits (I) THE INVERTER Outline • Introduction to digital circuits –The inverter • NMOS inverter with resistor pull-up Reading Assignment: Howe and Sodini; Chapter 5, Sections 5.1-5.3 16.012 Spring 2009 Lecture 111. Introduction to digital circuits: the inverter In digital circuits, digitally-encoded information is represented by means of two distinct voltage ranges: V VMAX VOH VOL logic 0 VMIN logic 1 undefined � region The Static Definition • Logic 0: VMIN V VOL • Logic 1: VOH V VMAX • Undefined logic value: VOL V VOH Logic operations are performed using logic gates. Simplest logic operation of all: inversion inverter 26.012 Spring 2009 Lecture 11Ideal inverter IN OUT 1OUT=IN 0 1 IN 0 Circuit representation and ideal transfer function: VOUT v+ V+ VOUT=VIN V+ + +2 VOUTVIN --0 0 V�M=V+ V+ VIN 2 Define switching point or logic threshold : • VM input voltage for which VOUT = VIN – For 0 VIN < VM VOUT = V+ – For VM < VIN V+ VOUT = 0 Ideal inverter returns well defined logical outputs (0 or V+) even in the presence of considerable noise in VIN (from voltage spikes, crosstalk, etc.) signal is regenerated! 6.012 Spring 2009 Lecture 11 3“Real” inverter • Logic 0: –VMIN output voltage for which VIN = V+ –VOL smallest output voltage where slope = -1 • Logic 1: –VOH largest output voltage where slope = -1 –VMAX output voltage for which VIN = 0 In a real inverter, valid logic levels defined as follows: VOUT VINV+ 0 0 slope=-1VOH VOL VMIN VMAXlogic 1 logic 0 transition � region 46.012 Spring 2009 Lecture 11Two other important voltages: Define: VIL smallest input voltage where slope = -1 VIH highest input voltage where slope = -1 If range of output values VOL to VOH is wider than the range of input values VIL to VIH, then the inverter exhibits some noise immunity. (|Voltage gain| > 1) Quantify this through noise margins. V OUT V INV + 0 0 slope=-1 V OH V IL V IH V OL V MIN V MAX range of input values�that produce valid logic 0range of input values�logic 1 logic 0 undefined � region that produce valid logic 1 56.012 Spring 2009 Lecture 11Chain of two inverters: Define noise margins: NMH VOH - VIH noise margin high NML VIL - VOL noise margin low noise M N inverter M� output inverter N� input VOH VOUT VIN NMH NMLVOL VIH VIL 66.012 Spring 2009 Lecture 11Simplifications for hand calculations: Logic levels and noise margins • Assume VOL VMIN and VOH VMAX • Trace tangent of transfer function at VM – Slope = small signal voltage gain (Av) at VM •VIL intersection of tangent with VOUT = VMAX •VIH intersection of tangent with VOUT = VMIN It is hard to compute points in transfer function with slope = -1. Approximate in the following way: VOUT VIHVIL VM VM VINV+ 0 0 VOL=VMIN VOH=VMAX VOUT=VIN slope= Av 76.012 Spring 2009 Lecture 11Transient Characteristics Inverter switching in the time domain: tR rise time between 10% and 90% of total swing tF fall time between 90% and 10% of total swing tPHL propagation delay from high-to-low between 50% points tPLH propagation delay from low-to-high between 50% points VOL 90% 50% 10% tPHL tPLH VOH tR tCYCLE 50% 90% 10% 0 t VIN VOUT 0 t tR tF VOH VOL tF Propagation delay: tP = 1 2 tPHL + tPLH ( ) 86.012 Spring 2009 Lecture 11Simplifications for hand calculations: Propagation delay • Consider input waveform is an ideal square wave • Propagation delay times = delay times to 50% point • SPICE essential for accurate delay analysis VOH VOH VOL VIN VOUT tPHL tPLH VOH VOL 50% t t tCYCLE tCYCLE 96.012 Spring 2009 Lecture 112. NMOS inverter with “pull-up” resistor •VBS = 0 (typically not shown) •CL summarizes capacitive loading of the following stages (other logic gates, interconnect lines, etc.) • If VIN < VT, MOSFET is OFF – VOUT = VDD • If VIN > VT, MOSFET is ON – VOUT small – Value set by resistor / nMOS divider Basic Operation: Essential features: VIN VOUT V+ =VDD IR ID CL R load capacitance (from following� stages) 106.012 Spring 2009 Lecture 11Transfer function obtained by solving: IR = ID Can solve graphically: I–V characteristics of load: VIN VR VOUT VDD IR ID R + -116.012 Spring 2009 Lecture 11Overlap I–V characteristics of resistor pull-up on I–V characteristics of transistor: Transfer function: VDS VGS=VDD VGS=VIN VGS=VT 0 0 IR=ID VDD VDD R load line VOUT=VDS VIN=VGS 0 0 � VDDVT VDD =VOUT 126.012 Spring 2009 Lecture 11For VMAX, transistor is cut-off, ID = 0: VMAX = VDD For VMIN, transistor is in linear regime; solve: ID = W L μnCox VDD VMIN 2 VT VMIN = IR = VDD VMIN R I D = W 2L μnCox VM VT( )2 = I R = VDD VM R For VM, transistor is in saturation; solve: Logic levels: VOUT=VDS VOUT=VIN VIN=VGS 0 0 � VDDVT VM VM VMAX=VDD VMIN 136.012 Spring 2009 Lecture 11Small signal equivalent circuit model at VM (transistor in saturation): Av = vout vin = gm ro // R( ) gmR Noise Margins: VOUT=VDS VOUT=VIN VIN=VGS 0 0 � VDDVT VMAX=VDD VMIN Av G S D + -vin + -vgs + -voutgmvgs ro R + -vin + -voutgmvin (ro//R) 146.012 Spring 2009 Lecture 11What did we learn today? Summary of Key Concepts • Logic circuits must exhibit immunity to noise in the input signal – Noise margins • Logic circuits must be regenerative – Able to restore clean logic values even if input is noisy. • Propagation delay: time for logic gate to perform its function. • Concept of load line: graphical technique to visualize transfer characteristics of inverter. • First-order solution (by hand) of inverter figures-of-merit easy if regions of operation of transistor are correctly identified. • For more accurate solutions, use SPICE (or other CAD tool). 156.012 Spring 2009 Lecture 11MIT OpenCourseWarehttp://ocw.mit.edu 6.012 Microelectronic Devices and Circuits Spring 2009 For information about citing these materials or our Terms of Use, visit:
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