6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 21-1 Lecture 21 - Multistage Amplifiers (I) Multistage Amplifiers November 22, 2005 Contents: 1. Introduction 2. CMOS multistage voltage amplifier 3. BiCMOS multistage voltage amplifier 4. BiCMOS current buffer 5. Coupling amplifier stages Reading assignment: Howe and Sodini, Ch. 9, §§9.1-9.36.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 21-2 Key questions • How can one build a wide range of high-performance amplifiers using the single-transistor stages studied so far? • What are the most important considerations when assembling mulstistage amplifiers: – regarding interstage loading? – regarding interstage biasing?6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 21-3 1. Introduction Amplifier requirements are often demanding: • must adapt to specific kinds of signal source and load, • must deliver sufficient gain Single-transistor amplifier stages are very limited in what they can accomplish ⇒ multistage amplifier. VDD vs VS RS VSS signal source vOUT RL + -signal load Issues: • What amplifying stages should be used and in what order? • What devices should be used, BJT or MOSFET? • How is biasing to be done?6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 21-4 2 Summary of single stage characteristics: stage Avo,Gmo ,Aio CS Gmo = gm CD Avo gm gm+gmb CG Aio −1 Rin ∞ ∞ 1 gm+gmb Rout key function ro//roc transcond. amp. 1 voltage buffer gm+gmb roc//[ro (1 + gmRS )] current buffer CE Gmo gm rπ CC Avo 1 rπ + β(ro//roc//RL) CB Aio −1 1 gm ro//roc transcond. amp. 1 + RS voltage buffer gm β roc//{ro[1 + gm(rπ //RS )]} current buffer 2 Key differences between BJT’s and MOSFETs: BJT MOSFET IB = IC β IG =0 � gm = qIC kT >gm = 2W L µCoxID ro = VA IC >ro = 1 λID6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 21-5 2. CMOS multistage voltage amplifier 2 Goals: • high voltage gain • high Rin • low Rout 2 Good starting point: CS stage + -+ -vinvs RS + -vout-gm(ro//roc)vin ro//roc + -RL • Rin = ∞ • Avo = −gm(ro//roc), probably insufficient • Rout = ro//roc, too high6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 21-6 2 Add second CS stage to get more gain: + -+ -vin1vs RS + -vout1=vin2-gm1(ro1//roc1)vin1 ro1//roc1 + -+ -+ -vout2-gm2(ro2//roc2)vin2 ro2//roc2 RL • Rin = ∞ • Avo = gm1(ro1//roc1)gm2(ro2//roc2) • but Rout = ro2//roc2, still high 2 Add CD stage at output: vs ro2 ⎢⎢roc2 vin Avovin gm3 + gmb3RS CS − CS CD + + − vin3 vin3 + vout + −−− + − + − 1 gm3 + gmb3 gm3 RL • Rin = ∞ • Avo = gm1(ro1//roc1)gm2(ro2//roc2) gm3 , still high gm3+gmb3 • Rout = 1 , now small gm3+gmb36.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 21-7 3. BiCMOS multistage voltage amplifier 2 Avo(CE) >Avo(CS) because ro(BJ T ) >ro(MOSF ET ) and gm(BJ T ) >gm(MOSF ET ) but... CS stage is best first stage, since Rin = ∞. 2 Add CE stage following CS stage? vs vout RL RS CS CE vin1 rπ2 + − + − ro1 ⎢⎢roc1 Avo1vin1 Avo2vin2 ro2 ⎢⎢roc2 + − + − + − + − vin2 Trouble is interstage loading degrades gain: Rout1 = ro1//roc1 Rin2 = rπ2 Voltage divider between stages: Rin2 rπ2 rπ2 = 1 Rout1 + Rin2 ro1//roc1 + rπ2 ro1//roc1 Additional gain provided by CE stage more than lost in interstage loading.6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 21-8 2 Use two CS stages, but add CC stage at output: vs RS CS − CS CC vin rπ3 +β3(ro3 ⎢⎢roc3 ⎢⎢RL) + − vout + − vin3 ro2 ⎢⎢roc2 Avo1Avo2vin ro2 ⎢⎢roc2 + − + − + − gm3 β3 +1 + − vin3 RL Interstage loading: Rout2 = ro2//roc2,Rin3 = rπ3 + β3(ro3//roc3//RL) Then, interstage loss: Rin3 rπ3 + β3(ro3//roc3//RL) = Rout2 + Rin3 ro2//roc2 + rπ3 + β3(ro3//roc3//RL) better than trying to use a CE stage, but still pretty bad. Benefit is that Rout has improved: 1 Rout2 1 ro2//roc2Rout = Rout3 = + = + gm3 β3 gm3 β3 Since, in general, gm(BJ T ) >gm(MOSF ET ), Rout could be better than CD output stage if ro2//roc2 is not too large. Otherwise, CD stage output is better.v6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 21-9 2 Better voltage buffer: cascade CC and CD output stages. What is best order? Since Rin(CD)= ∞, best to place Avo1Avo2vin ro2 ⎢⎢roc2 vin vin3 vin3 vin4 vin4 vout CS − CS CD − CC rπ4 +β4(RL ⎢⎢ro4 ⎢⎢roc4) gm3 + gmb3 β4(gm3 + gmb3) 1 RL RS 1 gm4 1 + + − + − + − + + − + − + − + − − CD first: s Interstage loading: Rin3 =1 Rout2 + Rin3 Rin4 rπ4 + β4(ro4//roc4//RL) = 1 Rout3 + Rin4 gm3+1 gmb3 + rπ4 + β4(ro4//roc4//RL) and excellent output resistance: 1 Rout3 1 1 Rout = Rout4 = + = + gm4 β4 gm4 β4(gm3 + gmb3)6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 21-10 4. BiCMOS current buffer 2 Goals: • Unity current gain • very low Rin • very high Rout Start with common-base stage: iin is RS -iin1/gm RL iout roc//(βro) • Aio = −1 • Rin = 1 gm • Rout = roc//{ro[1 + gm(rπ//RS )]} Note that if RS is not too low, Rout roc//(βro). Can we further increase Rout by adding a second CB stage?The base current limitsumber of CB that v6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 21-11 2 CB-CB current buffer: is RLRS iout −iin1 −iin2 iin2iin1 [ gm2ro2(rπ2 ⎢⎢β1ro1 ⎢⎢roc1)] ⎢⎢roc2 CB CB β1ro1 ⎢⎢roc1gm1 1 gm2 1 Now Rout = Rout2 = roc2//{ro2[1 + gm2(rπ2//Rout1)]} Plugging in Rout1 roc1//(β1ro1), Rout = roc2//{ro2[1 + gm2(rπ2//roc1//β1ro1)]} But, since rπ2 roc1//(β1ro1), then Rout roc2//[ro2(1 + gm2rπ2)] roc2//(β2ro2) Did not improve anything! the n stages impro e Rout to just one. The base current limits thenumber of CB stages that improveRoutto just one.Since CG stage has no gate current, cascade it behind CB stage.6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 21-12 2 CB-CG current buffer: is RLRS iout −iin1 −iin2 iin2iin1 [gm2ro2(β1ro1 ⎢⎢roc1)] ⎢⎢roc2 CB CG β1ro1 ⎢⎢roc1gm1 1 gm2 1 Rout = Rout2 = roc2//[ro2(1 + gm2Rout1)] with Rout1 roc1//(β1ro1), Rout = roc2//[ro2gm2(roc1//β1ro1)] Now Rout has improved by about gm2ro2, but only to the extent that roc2 is high enough...6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 21-13 5. Coupling amplifier stages 2
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