6.012 - Microelectronic Devices and Circuits Lecture 13 - Linear Equivalent Circuits - Outline • Announcements Exam Two - Coming next week, Nov. 5, 7:30-9:30 p.m. • Review - Sub-threshold operation of MOSFETs • Review - Large signal models, w. charge stores p-n diode, BJT, MOSFET (sub-threshold and strong inversion) • Small signal models; linear equivalent circuitsGeneral two, three, and four terminal devices pn diodes: Linearizing the exponential diode Adding linearized charge stores BJTs: Linearizing the F.A.R. β-model Adding linearized charge stores MOSFETs: Linearized strong inversion model Linearized sub-threshold model Adding linearized charge stores Clif Fonstad, 10/27/09 Lecture 13 - Slide 1Sub-threshold Operation of MOSFETs, cont. - The barrier at the n+-p junction is lowered near the oxide-Si Clif Fonstad, 10/27/09 Lecture 13 - Slide 2 interface for any vGS > VFB. - The barrier is lowered by φ(x) - φp for 0 < x < xD. (This is the effective vBE on the lateral BJT between x and x + dx.) - The barrier lowering (effective forward bias) (1) is controlled by vGS, and (2) decreases quickly with x. D B S G n+ n+ p tn+ x y0 L vBS = 0 xD y φn+ φp 0 L φ(x) φ(x)-φp -φp φp -tox xxd φm vGS - φp φ(0) vBE,eff(x) = [φ(x)− φp] Plot vs x at fixed y, 0 < y < L. φ(x) Injection occurs over this range, but is largest near x = 0. -tox 0 vDS > 0 Injection VFB < vGS < VT Plot vs y at fixed x, 0 < x < xD. φ(0,y) φn++ vDSSub-threshold Operation of MOSFETs, cont. - To calculate iD, we first find the current in each dx thick slab: DS G -tox 0 x y0 L vDS > 0 xD VFB < vGS < VT n+ n+ p x x+dx ! n' x,0( )= nieq"(x,vGS)/kT#1( )$ nieq"(x,vGS)/kT! n' x,L( )" n' x,0( )e#qvDS/kTvBS = 0 ! diD(x) = qDen'(x,0)" n'(x,L)LW dx #WLDeqni1" e"qvDS/kT )( )eq$(x,vGS)/kTdxClif Fonstad, 10/27/09 Lecture 13 - Slide 3Sub-threshold Operation of MOSFETs, cont. - Integrating this from x = 0 to x = xD using the approximate value for the integral derived in Lecture 9, and approximating the relationship between Δφ(0) and ΔvGS as linear, i.e. Δφ(0) ≈ ΔvGS/n, we arrived at: ! iD, s"t(vGS,vDS,0) #WLµeCox*kTq$ % & ' ( ) 2n"1[ ]eq vGS"VT{ }nkT1" e"qvDS/ kT( )! n " 1+1Cox*#SiqNA2 $2%p[ ]& ' ( ) ( * + ( , ( =-where Variations on this form: It is common to see iD,s-t written using the factors K and γ we defined earlier, and with kT/q replaced by Vt, the thermal voltage, and [n -1] replaced in the pre-factor. Written this way, we have: Clif Fonstad, 10/27/09 Lecture 13 - Slide 4 ! iD,s"t(vGS,vDS,0) # K Vt2$2 "2%p[ ]evGS"VT{ }nVt1" e"vDS/Vt( )! "#2$SiqNACox*, K #WLµeCox*, n(vBS) % 1+"2 &2'p& vBS[ ]( ) * + * , - * . * withSub-threshold Output Characteristic - We plot a family of iD vs vDS curves with (vGS - VT) as the family variable, after first defining the sub-threshold diode saturation current, IS,s-t: ! IS,s"t# K Vt2$2 "2%p[ ]= KVt2n "1[ ]log iD,s-t vDS 10-1 IS,s-t 10-2 IS,s-t 10-3 IS,s-t 10-4 IS,s-t (vGS-VT) = -0.06xn Volts (vGS-VT) = -0.12xn Volts (vGS-VT) = -0.18xn Volts (vGS-VT) = -0.24xn Volts ! iD,s"t(vGS,vDS,0) # IS,s"tevGS"VT{ }nVt1" e"vDS/Vt( )Clif Fonstad, 10/27/09 Lecture 13 - Slide 5Large Signal Model for MOSFET Operating Sub-threshold - The large signal model for a MOSFET operating in the weak inversion or sub-threshold region looks the same model as that for a device operating in strong inversion (vGS > VT) EXCEPT there is a different equation relating iD to vGS, vDS, and vBS: We will limit our model to and ! vGS" VT,vDS> 3VtvBS= 0.! iD,s"t(vGS,vDS,0) # IS,s"t1"$vDS( )evGS"VTo{ }nVt1" e"vDS/Vt( )! iG,s"t(vGS,vDS,vBS) = 0≈ 1 for vDS > 3 VtGS,BDiD(vGS, vDS)iG (= 0)iD Early effect Clif Fonstad, 10/27/09 Lecture 13 - Slide 6Large signal models with charge stores: p-n diode: BJT: npn (in F.A.R.) MOSFET: n-channel Clif Fonstad, 10/27/09 GSDqDBiDBqSBqGqBCBECiB’IBS!FiB’qBEBAIBSqABqAB: Excess carriers on p-side plus excess carriers on n-side plus junction depletion charge. qBE: Excess carriers in base plus E-B junction depletion charge qBC: C-B junction depletion charge qG: Gate charge; a function of vGS, vDS, and vBS. qDB: D-B junction depletion charge qSB: S-B junction depletion charge Lecture 13 - Slide 7Signal notation: A transistor circuit, whether digital or analog, is typically connected to several DC power supplies that establish the desired DC "bias" currents and voltages throughout it. It also typically has one or more time varying input signals that result in time varying currents and voltages (one of which is the desired output of the circuit) being added to the DC bias currents and voltages. Each voltage and current in such a circuit thus has a DC bias portion and a signal portion, which add to make the total. We use the following notation to identify these components and the total: Total: lower-case ! iA(t) = IA+ ia(t)vAB(t) = VAB+ vab(t)Signal: lower-case letter and upper-Bias: upper-caseletter and subscript. case subscript. letter and subscript. Clif Fonstad, 10/27/09 Lecture 13 - Slide 8DC Bias Values: To construct linear amplifiers and other linear signal process-ing circuits from non-linear electronic devices we must use regions in the non-linear characteristics that are locally linear over useful current and voltage ranges, and operate there. To accomplish this we must design the circuit so that the DC voltages and currents throughout it "bias" all the devices in the circuit into their desired regions, e.g. yield the proper bias currents and voltages: ! IA, IB, IC, ID,etc. VAG,VBG,VCG,VDG,etc.and This design is done with the signal inputs set to zero and using the large signal static device models we have developed for the non-linear devices we studied: diodes, BJTs, MOSFETs. Working with these models to get the bias values, though not onerous, can be tedious. It is not something we want to have to do to find voltages and currents when the signal inputs are applied. Instead we use linear equivalent circuits . Clif Fonstad, 10/27/09 Lecture 13 - Slide 9Linear equivalent circuits: After biasing each non-linear devices at the proper point the signal currents and voltages throughout the circuit will be linearly related for small enough input signals. To calculate how they are related, we make use of the linear equivalent circuit (LEC) of our circuit. The LEC of any circuit is a combination of linear circuit elements (resistors, capacitors, inductors, and dependent sources) that correctly models and predicts the
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