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MIT 6 012 - Lecture 13 - Digital Circuits (II) MOS Inverter Circuits

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6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-1Lecture 13 - Digital Circuits (II)MOS Inverter CircuitsOctober 25, 2005Contents:1. NMOS inverter with resistor pull-up (cont.)2. NMOS inverter with current-source pull-up3. Complementary MOS (CMOS) InverterReading assignment:Howe and Sodini, Ch. 5, §5.36.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-2Key questions• What are the key design trade-offs of the NMOS in-verter with resistor pull-up?• How can one improve upon these trade-offs?• What is special about a CMOS inverter?6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-31. NMOS inverter with resistor pull-up (cont.)VINVOUTV+=VDDIRIDCLRVOUT=VDSVOUT=VINVIN=VGS00VDDVTVOH=VMAX=VDDVOL=VMINVMVILVIHVMslope= Av(VM)2 Noise margins:NML= VIL− VOL= VM−VMAX− VM|Av(VM)|− VMINNMH= VOH−VIH= VMAX−VM(1+1|Av(VM)|)+VMIN|Av(VM)|Need to compute |Av(VM)|.6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-4Small-signal equivalent circuit model at VM(transistor insaturation):GSD+-vin+-vgs+-voutgmvgsroR+-vin+-voutgmvinro//Rvout= −gmvin(ro//R)Then:Av=voutvin= −gm(ro//R) '−gmRThen:|Av(VM)| = gm(VM)RFrom here, get NMLand NMHusing above formulae.6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-52 Dynamics• CLpull-down limited by current through transistor[will study in detail with CMOS]• CLpull-up limited by resistor (tPLH∼ RCL)• pull-up slowestVIN:LO HIVIN:HI LOVOUT:HI LOVOUT:LO HIVDDCLRVDDCLRpull-downpull-up6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-62 Inverter design issues:noise margins ↑⇒|Av|↑⇒• R ↑⇒ RCL↑⇒slow switching• gm↑⇒ W ↑⇒big transistor(slow switching at input)Trade-off between speed and noise margin.During pull-up, need:• high current for fast switching,• but also high resistance for high noise margin.⇒ use current source as pull-up.6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-72. NMOS inverter with current-source pull-upI-V characteristics of current source:iSUPISUPvSUP1rocvSUPiSUP+_00Equivalent circuit models:ISUProciSUPvSUP+_roclarge-signal model small-signal model• high current throughout voltage range: iSU P' ISU P• high small-signal resistance, roc.6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-8NMOS inverter with current-source pull-up:VINVOUTVDDCLiSUPVDSVGS=VDDVGS=VINVGS=VT00iSUP=IDVDDload lineISUPTransfer characteristics:VOUTVIN00VDDVTVDDHigh roc⇒ high noise margin6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-9Dynamics:VIN:LO HIVOUT:HI LOVOUT:LO HIVDDCLiSUPVDDCLiSUPpull-downpull-upVIN:HI LOFaster pull-up b ecause capacitor charged at constant cur-rent.6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-102 PMOS as current-source pull-upI-V characteristics of PMOS:VSDp-IDpIDpVSGpVSGp=-VTp00VSGp-IDp-VTp00saturationSGDNote: enhancement-mode PMOS has VTp< 0.In saturation:−IDp∝ ( VSG+ VTp)26.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-11Circuit and load-line diagram of inverter with PMOS cur-rent source pull-up:VINVBVOUTVDDCLVOUTVDDVIN00-IDp=IDnVDDPMOS load line for VSG=VDD-VBTransfer function:VOUTVIN00VDDVTnVDDNMOS cutoffPMOS triodeNMOS saturationPMOS triodeNMOS saturationPMOS saturationNMOS triodePMOS saturation6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-12Noise margin:• compute VM= VIN= VOUT• compute |Av(VM)|At VMboth transistors saturated:IDn=Wn2LnµnCox(VM− VTn)2−IDp=Wp2LpµpCox(VDD− VB+ VTp)2And:IDn= −IDpThen:VM= VTn+vuuuuuuutµpWpLpµnWnLn(VDD− VB+ VTp)6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-13Small-signal equivalent circuit model at VM:G1S1D1+-vin+-vgs1+-voutgmnvgs1ron+-vin+-voutgmnvinron//ropG2S2D2+-vsg2=0gmpvsg2ropAv= −gmn(ron//rop)6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-14NMOS inverter with current-source pull-up allows fastswitching with high noise margins.But... when VIN= VDD, there is a direct current pathbetween supply and ground⇒ power consumption even if inverter is idling.VIN:HIVBVOUT:LOVDDCLVOUTVDDVIN00-IDp=IDnVDDPMOS load line for VSG=VDD-VBWould like to have current source that is itself switchable,i.e., it shuts off when input is high ⇒ CMOS!6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-15Screen shots of NMOS inverter transfer characteristics:2 NMOS inverter with resistor pull-up2 NMOS inverter with current source pull-up6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-163. Complementary MOS (CMOS) InverterCircuit schematic:VINVOUTVDDCLBasic operation:•VIN=0⇒ VOUT= VDDVGSn=0<VTn⇒ NMOS OFFVSGp= VDD> − VTp⇒ PMOS ON•VIN= VDD⇒ VOUT=0VGSn= VDD>VTn⇒ NMOS ONVSGp=0< −VTp⇒ PMOS OFFNo power consumption while idling in any logic state.6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-17Output characteristics of both transistors:VSDp-IDpVSGpVSGp=-VTp00VDSnVGSnVGSn=VTn00IDnNote:VIN= VGSn= VDD− VSGp⇒ VSGp= VDD− VINVOUT= VDS n= VDD− VSDp⇒ VSDp= VDD− VOUTIDn= −IDpCombine into single diagram of IDvs. VOUTwith VINasparameter.6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-18VINVOUTVDDCLVOUTVIN00VDD-VINID? no current while idling in any logic state.Transfer function:VOUTVIN00VDDVTnVDD+VTpVDDNMOS cutoffPMOS triodeNMOS saturationPMOS triodeNMOS saturationPMOS saturationNMOS triodePMOS saturationNMOS triodePMOS cutoff? ”rail-to-rail” logic: logic levels are 0 and VDD? high |Av| around logic threshold ⇒ good noise margins6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-19Transfer characteristics of CMOS inverter in WebLab:6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-20Key conclusions• In NMOS inverter with resistor pull-up: trade-off be-tween noise margin and speed.• Trade-off resolved using current-source pull-up: usePMOS as current source.• In NMOS inverter with current-source pull-up: if VIN=HI, power consumption even if inverter is idling.• Complementary MOS: NMOS and PMOS switch al-ternatively ⇒– no power consumption while idling– ”rail-to-rail ” logic: logic levels are 0 and VDD– high |Av| around logic threshold ⇒ good


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MIT 6 012 - Lecture 13 - Digital Circuits (II) MOS Inverter Circuits

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