1 MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Science6.012 Microelectronic Devices and Circuits – Fall 2009 SPECIAL PROBLEM ON CIRCUIT DESIGN – 12/1/09 edition Issued: Wednesday, November 18, 2009; updated Dec. 1. Due: Friday, December 4, 2009 and on (be sure that your name is checked off the master list as you hand in your solution). Late solutions will receive zero points; see I.5 below. Updates: Issues will be dealt with as needed; watch your e-mail. I. General Comments Do not panic when you see the circuit. It looks overwhelming at first but it is made up of simple building-block pieces and it is understandable. In addition, you will be given help along the way, first by this write-up, and later in recitations, lectures, and additional handouts. At the same time, the designprocess you need to go through is a complex one and it is not one you willsuccessfully negotiate in one sitting. Thus it is important that you get started,first developing an understanding of the circuit and the nature of the designchallenge, and then at doing your design. You can do it, but not in one night. II. The Ground Rules 1. Consider this design problem more like an open book exam, than a problem set. You are encouraged to consult references and to seek guidance from the6.012 staff, and to discuss design issues with others, but you should not work on your specific design and write-up with any other students or any other individuals. Nor should you compare design values or performance results with other students. The design you submit must be your own; any collaborations(and they should be minor) should be noted. 2. Do not let the design slide until the last week. Make a first attempt at asolution early so you can obtain any clarification and guidance you may needfrom the 6.012 staff before the Thanksgiving holiday (Nov. 26-29). 3. You are required to submit a completed Excel file cover sheet, and a detaileddiscussion of your design and your approach to arriving at it. The Excel file cover sheet will be available on Stellar. Your write-up should include circuitdiagrams for your large signal and incremental analyses, and the equations youused and calculations you made. It should also include a discussion of the trade-offs you considered in your design. View the minimum performance objectivesas a challenge and try to do even better. 4. Make reasonable approximations. Do not carry your calculations out to any more than three (3) significant figures. Your predicted performance valuesshould also be stated to no more than three (3) significant figures. The following are examples of numbers with three significant figures: 1.23, 0.123, 123, 3450, 0.0345, 6.78 x 109.2 5. Anyone who does not submit a design problem solution which demonstratesa reasonable level of effort will automatically receive zero points and a grade of"I" for 6.012 (as long as their performance is otherwise passing). An "I" received for this reason can only be completed by submitting an acceptable solution to this term's design problem by January 15, 2010. Late solutions will be checked todetermine that they are acceptable, but will receive zero points for purposes ofdetermining an overall course grade. III. Design Objective Your design objective is to specify transistor dimensions for the integratedlinear amplifier shown in Figure 1 on Page 3 so that it meets or, hopefully,exceeds the performance objectives itemized below. You are able to increase MOSFET gate widths and/or lengths and BJT areas by integer multiples. The circuit, which is described in full detail in Section V, is a BiCMOSdifferential amplifier designed to have a large differential-mode gain, large common-mode rejection ratio, large common mode input voltage range, and large output voltage swing. You are to specify the dimensions of the devices in the circuit in Figure 1, andto calculate the corresponding bias levels and performance characteristics. You are also expected to discuss the main aspects of your design in your solution write-up, and to also discuss there the factors you took into consideration inarriving at your design. Performance Objectives: 1) Small signal gains defined by writing vout = Avc(vin1+vin2)/2 + Avd(vin1 -vin2) a) Small-signal differential-mode voltage gain, Avd, into a 50 Ω load: as large as possible, and not less than 125,000 b) Small-signal common-mode voltage gain, Avc, into a 50 Ω load: as small as possible, and not more than 0.002 2) Common-mode rejection ratio, Avd/Avc : ≥ 5 x 107 3) Small-signal output resistance, rout: ≤ 10 Ω. 4) Maximum output voltage swing into a 50 Ω load, |vOUT|max: ≥ 0.75 V. 5) Minimum common-mode input voltage range, |vIC|min: ≥ 0.75 V. 6) Total quiescent power dissipation not to exceed 8.5 mW. 7) Output Voltage, i.e. the quiescent voltage at the output, i.e. vOUT, when vIN = 0, in a feedback circuit like that illustrated to the right assuming perfect element matching: |VOUT| ≤ 20 µV. +-50 !R+-RvOUTvIN+-AvdInput 1Input 234 IV. Component Specifications A. Transistors All of the MOSFETs in this amplifier should be operated in strong inversion(as opposed to sub-threshold). Some of the transistors in the circuit can be chosen to be the smallest devices that can be made with the fabrication processused, but others will have to be designed to be larger; this might be done toadjust the value of a current source, for example, or to maximize the gain of a stage. In the listing below the properties of the minimum size devices are listedfirst and then the scaling rules for designing larger devices are given. 1. npn Bipolar Transistors -- The npn transistors are vertical structures that have the following large-signal and small-signal (hybrid-π) parameters a) Minimum size devices i) βF = 200 ii) IC = 100 µA when VBE = 0.6 V (i.e. IES = 10-14 A) VCE,sat = 0.3 V iii) gm = qIC/kT, gπ = gm/βF go = IC/|VA| with |VA| = 50V iv) Operating range: 1.0 µA ≤ IC ≤ 3 mA b) Scaled devices -- You may increase the base-emitter junction area by up to a factor of 25 times. Increasing the base-emitter junction area, AE, by a
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