6.012 - Microelectronic Devices and Circuits Lecture 15 - Digital Circuits: CMOS - Outline • Announcements One supplemental reading on Stellar Exam 2 - Thursday night, Nov. 5, 7:30-9:30 • Review - Inverter performance metrics Transfer characteristic: logic levels and noise margins 2) Power: Pave, static + Pave, dynamic (= IONVDD/2 + f CLVDD Switching speed: charge thru pull-up, discharge thru pull-down If can model load as linear C: dvOUT/dt = iCH(vOUT)/CL; = iDCH(vOUT)/CL If can say iCH, iDCH constant: τHI-LO = CL(VHI-VLO)/ICH ; τHI-LO = CL(VHI-VLO)/IDCH Fan-out, fan-in (often only 10 to 90% swings) Manufacturability • CMOS Transfer characteristic Gate delay expressions Power and speed-power product • Velocity SaturationGeneral comments Impact on MOSFET and Inverter Characteristics Clif Fonstad, 11/3/09 Lecture 15 - Slide 1Transfer characteristic Node equation: iPD = iPU 0 for vIN < VPull-UpVDD++––iPUvOUTvINiPDT,PD iPD = KPD(vIN-VT,PD)2/2 for vIN-VT,PD < vOUT KPD(vIN-VT,PD -vOUT/2) vOUT forvIN-VT,PD > vOUT iPU: Depends on the device used Gives us: VHI and VLO NML and NMH Switching transients Pull-UpVDDHI to LO++––CLLO to HIOFFiPUGeneral approach: The load, CL, is a non-linear charge store, but for MOSFETs it is fairly linear and it is useful to think linear: dvout/dt ≈ iCL/CL Bigger current Clif Fonstad, 11/3/09 Lecture 15 - Slide 2 → faster vOUT change Charging cycle: Discharging cycle:iCharge = iPU iDischarge = iPD – iPU VLOV1LV1HVHIVHIVLOVMVMVINVOUTNMLNMHPull-UpVDD++––CLHI to LOLO to HIONiPUiPDiDischargePull-UpVDDvOUTvIN++––CLVDDvOUTvIN++––VDDvOUTvIN++––VGG(>>VDD)VDDvOUTvIN++––VDDvOUTvIN++––VDDvOUTvIN++––RLMOS inverters: 5 pull-up Resistor pull-up choices Generic inverter n-channel, e-mode pull-up n-channel, d-mode Active p-channel VDD on gate VGG on gate pull-up (NMOS) pull-up (CMOS)** Clif Fonstad, 11/3/09 Lecture 15 - Slide 3 * Known as PMOS when made with p-channel. ** Notice that CMOS has a larger (~3x) input capacitance.Switching transients: summary of charge/discharge currents VDDvOUTvIN++––VGG(>>VDD)VDDvOUTvIN++––RLResistor and E-mode pull-up (VGG on gate) E-mode pull-up (VDD on gate) D-mode pull-up (called "NMOS") VDDvOUTvIN++––VDDvOUTvIN++––CMOS Clif Fonstad, 11/3/09 VDDvOUTvIN++––Lecture 15 - Slide 4 vOUTVDDIONiDischargeiPD = iDischarge + iPUvOUTVDDIONiDischargeiPD = iDischarge + iPUvOUTVDDIONiDischargeiPD = iDischarge + iPUvOUTVDDIONiDischargeiPD = iDischarge + iPUION = 0vOUTVDDIONiChargeiPU = iChargevOUTVDDIONiChargeiPU = iChargeiPU = iChargevOUTVDDIONiChargevOUTVDDIONiChargeiPU = iCharge• Comparisons made with same pull-down MOSFET, VHI, and ION.CMOS: transfer characteristic calculation VTnVDDVDDvINvOUTQnoffQn sat.Qn lin.vGSn= VTnvDSn = vGSn -VTnQn: VDDvOUTvIN++––Qn Qp QpoffQp sat.Qp lin.VDDVDD|VTp|vINvOUT(VDD+VTp)vSGp = vSDp-|VTp|vSGp =|VTp|Qp: VTnVDDVDD-VTpvINvOUT(VDD+VTp)IIIIIIIVVvGSn =VTnvDSn = vGSn -VTnvSGp =|VTp|vSDp = vSGp-|VTp|Transistor operating condition in each region: Region Qn Qp I cut-off linear II saturation linear III saturation saturation IV linear saturation V linear cut-off Clif Fonstad, 11/3/09 Lecture 15 - Slide 5CMOS: transfer characteristic calculation, cont. Clif Fonstad, 11/3/09 Lecture 15 - Slide 6 Region I: Region II: VDDvOUTvIN++––Qn Qp VTnVDDVDDvINvOUTIIIIIIIVVvGSn =VTnvDSn = vGSn -VTnvSGp =|VTp|vSDp = vSGp-|VTp||VTp|(VDD-|VTp|)! iDn= 0 and iDp= KpVDD" vIN" VTp"VDD" vOUT( )2# $ % & ' ( VDD" vOUT( )so iDn= iDp) vOUT= VDD! iDn= KnvIN"VTn"vOUT2# $ % & ' ( vOUT and iDp= 0so iDn= iDp) vOUT= 0CMOS: transfer characteristic calculation, cont. Region III: VDDvOUTvIN++––Qp ! iDn=Kn2vIN" VTn[ ]2 and iDp==Kp2VDD-vIN" VTp[ ]2so iDn= iDp# vIN=VDD" VTp+ VTnKnKp1+ KnKp. To achieve symmetry we makeKn= Kp, and VTp= VTn. With this: vIN=VDD2 and VDD2" VTn$ vOUT$VDD2+ VTpQn Regions II and IV:Parabolic segments connecting the three straight segments. Clif Fonstad, 11/3/09 Lecture 15 - Slide 7 VTnVDDVDD|VTp|vINvOUT(VDD- |VTp|)IIIIIIIVVvGSn =VTnvDSn = vGSn -VTnvSGp =|VTp|vSDp = vSGp-|VTp|VDD/2VDD/2-VTnVDD/2+|VTp|CMOS: transfer characteristic calculation, cont. Complete characteristic so far: VDDvOUTvIN++–– KpVTp KnVTnVTnVDDVDD-VTpVDD/2VINVOUT(VDD+ VTp)(VDD/2-VTp)(VDD/2-VTn)VDD/2NOTE: We design CMOS inverters to have Kn = Kp and VTn = -VTp to obtain the optimum symmetrical characteristic. Clif Fonstad, 11/3/09 Lecture 15 - Slide 8Clif Fonstad, 11/3/09 Lecture 15 - Slide 9 CMOS: transfer characteristic calculation, cont.VTnVDDVDD-VTpVDD/2vINvOUT(VDD- |VTp|) Our calculation says that the transfer characteristic is vertical in Region III. We know it must have some slope, but what is it? To see, calculate the small signal gain about the bias point: VIN = VOUT = VDD/2 Begin with the small signal model: gonsngmnvgsn+-vgsn = vin+-voutdngnsn+-vingopspgmpvgsp+-dpgpvgsp = vinspVDDVDD/2+vin++–– Kp !p VTpVDD/2+vout Kn !n VTnQpQnCMOS: transfer characteristic calculation, cont. Redrawing the circuit we get from which we see immediately ! Av"#vOUT#vINQ=voutvin= $gmn+ gmp[ ]gon+ gop[ ]gmpvingonsn,spgmnvin+-vgsn=vgsp+-voutdn,dpgopgn,gpsn,sp+-vinIn Lecture 13 we learned how to write the conductances in terms of the bias point as! gmn= 2KnIDn, gmp= 2KpIDp= gmn, gon="nIDn, gop="pIDp="pIDn which will enable us to express the gain in terms of the bias Clif Fonstad, 11/3/09 Lecture 15 - Slide 10 point, IDn (= |IDp|), and MOSFET parameters ! Av"#vOUT#vINQ= $2 2KnIDn%n+%p[ ]IDn= $2 2Kn%n+%p[ ]IDnCMOS: transfer characteristic calculation, cont. Returning to the transfer characteristic, we see that the slope in Region III is not infinite, but is instead: Lecture 15 - Slide 11 VDDVDDVDD/2vINvOUTVDD/2AvVTnVDDVDD-VTpVDD/2vINvOUT(VDD- |VTp|)VDD/2Av! Av"#vOUT#vINQ= $gmn+ gmp[ ]gon+ gop[ ]Final comment: A quick and easy way to approximate the transfer characteristic of a CMOS gate is to simply draw the three straight line portions in Regions I, III, and V: Clif Fonstad, 11/3/09CMOS: switching speed; minimum cycle time The load capacitance: CL • Assume to be linear • Is proportional to MOSFET gate area • In channel: µe= 2µh so to have Kn = Kp we must have Wp/Lp = 2Wn/Ln Typically Ln = Lp = Lmin and Wn = Wmin, so we also have Wp = 2Wmin ! CL" n WnLn+ WpLp[ ]Cox*= n WminLmin+ 2WminLmin[ ]Cox*= 3nWminLminCox*Charging cycle: vIN: HI to LO; Qn off, Qp on; vOUT: LO to HI •
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