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MIT 6 012 - Lecture Notes

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1 6.012 - Microelectronic Devices and Circuits, Fall 2009 - 10/5/09 posting CMOS Gate Delays, Power, and Scaling GATE DELAYS In the last lecture (Lec. 15) we calculated the gate de-lay for a symmetrical CMOS inverter with VTn = |VTp| ≡ VT, Co* xn = Co* xp ≡ Co* x, and Kn= Kp, in which both the n- and p-channel devices were mini-mum gate length devices, i.e., Ln = Lp = Lmin. The p-channel device was made twice as wide as the n-channel device to get the desired K equality, because we assumed µe = 2 µh. We found that the gate delay was given by: 4 CL VDD τGD ≈ Kn(VDD - VT)2 Replacing CL and Kn, to write this in terms of the devicedimensions, we found after a bit of simple algebra: 12 n 2 VDD τGD ≈ µe Lm in (VDD - VT)2 POWER There is zero static power in CMOS so the only con-tribution is the dynamic power Pave = CLVD2 Df where f is the operating frequency and CL is the loading capacitance. This load will be the average fan-out, n,times the input capacitance of a similar CMOS gate, plusany parasitic interconnect capacitance: CL = n Co* x (Lmin Wn + Lmin Wp) + Cparasitic2 = 3 n Co* x Lmin Wn + Cparasitic Neglecting Cparasitic, we can write Pave = 3 n Co* xLmin Wn VD2 Df MAXIMUM POWER The maximum power dissipation will occur when the gate is operated at its maximum frequency (bit rate), which is in turn proportional to 1/τGD. Thus we can say 21Pave max ∝ 3 n Co*xLmin Wn VD D τGD 1 Wn = 4 Lmin µe Co* x VDD (VDD - VT)2 1 = 4 Kn VDD (VDD - VT)2 The importance of keeping VDD small is quite evident from this expression, but the situation is not black andwhite because making VDD small makes τGD large; the same is true of making Kn small. The whole problem ofwhat to reduce how while maintaining high performanceand not frying the IC chips is a complex one and has led to the development of rules for scaling dimensions and volt-ages; we will discuss scaling rules after first looking at onemore important parameter, the maximum average powerdissipation per unit area. POWER DISSIPATION PER UNIT AREA In many situations the power dissipation per unitarea is more important than the total power dissipation.To estimate how this factor varies with the device dimen-sions we make the assumption that the density of devices3 in an integrated circuit increases inversely with the gate area, WnLmin. We have: Pave max µe Co*x Pdensity max ∝ WnLmin ∝ 4 Lm2 in VDD (VDD - VT)2 SCALING RULES We in general want to simultaneously reduce gate de-lays, decrease power dissipation, and increase packingdensity, while not exceeding a certain power density. The place we start is with a reduction of the gate length, butwe quickly find we must do more than that or we get intotrouble. For example, as the gate length is reduced, the oxidethicknesses and the junction depths (of the sources anddrains) must be reduced proportionally to obtain goodtransistor characteristics. One is essentially maintaining along, thin geometry consistent with the gradual channelapproximation, and this turns out to be just what is needed to get good saturation (flat curves; small go) of the device output (iD vs vDS) characteristics. Thus, if we re-duce the minimum gate length, Lmin, by a factor of s, wewill also want to reduce the gate oxide, tox, by the same factor. To increase the packing density futher, we also re-duce the gate width, W, by the same factor: Lmin → Lmin/s W → W/s tox → tox/s With these changes we find that our gate delay, averagepower, device density, and power density change as fol-lows: τGD → τGD/s24 Pave → s Pave Device Density → s2 Device Density Pdensity max → s3 Pdensity max Clearly this is a formula for disaster because the powerdensity will increase dramatically if we only scale dimen-sions. We either have to develop much better ways to getthe heat out of an IC chip and package, so we can toleratea higher power density, or we have to change more than the dimensions. Packaging and heat sinking have beenimproved, to be sure, but the big gain comes from scalingthe voltages as well as the dimensions. If we scale the supply and threshold voltages as follows: VDD → VDD/s VT → VT/s then we find: τGD → τGD/s Pave → Pave/s2 Device Density → s2 Device Density Pdensity max → Pdensity max This is clearly a much better situation. At the same time it must be noted that it is not as easy to scale the voltages as it might at first seem and it has taken longer to do so thanit has to reduce dimensions because of a number of fac-tors. The control over the threshold voltage must be im-proved which places more demands on the process line,and the noise margins decrease by a factor 1/s so noisesources on the chip must be reduced. Also, supply volt-ages are not totally arbitrary since they must be tied tostandard battery cells, which come in increments of roughly 1 Volt (they range from 1.1 to 0.9 V over their use-5 ful lifetime). Early bipolar and MOSFET logic used VDD's of 5 V, but this has recently been reduced to 3, 2, and, even, 1 V. Scaling examples: Parameter Scaling factor, s Lmin (µm) wn (µm) tox (nm) VDD (V) VT (V) Fan out K (µA/V2) t (ps) fmax (MHz) Pave/gate (µW) Density (kgates/cm2 @ 20 W/cm2 max) Intel Families 386 486 Pentium 1 2 3 1.5 0.75 0.5 10 5 3 30 15 9 5 3.3 2.2 1 - - 3 3 3 230 450 600 840 400 250 29 50 100 92 23 10 220 880 2,000 Sources: Professsor Jesus del Alamo and Intel6 Intel Pentium Families Parameter 486 Pentium generations Lmin (µm) 1.0 0.8 0.5 0.35 Scaling factor, s - 1 1.6 2.3 SRAM Cell - 111 44 21 Area (µm2) Die size (mm2) 170 295 163 91 fmax (MHz) 38 66 100 200 tox (nm) 20 10 8 6 Metal layers 2 3 4 4 Planarization SOG CMP CMP CMP Poly type n n, p n, p n, p Transistors CMOS BiCMOS BiCMOS BiCMOS Source: Dr. Leon D. Yau, Intel, MIT VLSI Seminar, Cambridge, MA,Oct. 8, 1996. (This table is meant to illustrate the trend; seethe companion posting for data from 2000.)MIT OpenCourseWarehttp://ocw.mit.edu 6.012 Microelectronic Devices and Circuits Fall 2009 For information about citing these materials or our Terms of Use, visit:


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MIT 6 012 - Lecture Notes

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