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MIT 6 012 - lecture13annotat

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6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-1 Lecture 13 - Digital Circuits (II) MOS Inverter Circuits October 25, 2005 Contents: 1. NMOS inverter with resistor pull-up (cont.) 2. NMOS inverter with current-source pull-up 3. Complementary MOS (CMOS) Inverter Reading assignment: Howe and Sodini, Ch. 5, §5.36.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-2 Key questions • What are the key design trade-offs of the NMOS in-verter with resistor pull-up? • How can one improve upon these trade-offs? • What is special about a CMOS inverter?6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-3 1. NMOS inverter with resistor pull-up (cont.) V+ =VDD VOUT=VDS VOH=VMAX=VDD R IR VOUT VMID VIN CL VOL=VMIN 0 VOUT=VINslope= Av(VM)0 VT VM VDD VIN=VGS VIL VIH 2 Noise margins: VMAX − VMNML = VIL − VOL = VM − − VMIN |Av(VM )| 1 VMIN NMH = VOH −VIH = VMAX −VM (1+ )+|Av(VM )| |Av(VM )| Need to compute |Av(VM )|.6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-4 Small-signal equivalent circuit model at VM (transistor in G S D + -vin + -vgs + -voutgmvgs ro R + -vin + -voutgmvin ro//R saturation): vout = −gmvin(ro//R) Then: Av = vout = −gm(ro//R) −gmR vin Then: |Av(VM )| = gm(VM )R From here, get NML and NMH using above formulae.6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-5 2 Dynamics • CL pull-down limited by current through transistor [will study in detail with CMOS] • CL pull-up limited by resistor (tPLH ∼ RCL) • pull-up slowest VIN: LO HI VIN: HI LO VOUT: HI LO VOUT: LO HI VDD CL R VDD CL R pull-down pull-uprade-off between eed and noise mar6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-6 2 Inverter design issues: noise margins ↑⇒|Av|↑⇒ • R ↑⇒ RCL ↑⇒slow switching • gm ↑⇒ W ↑⇒big transistor (slow switching at input) T sp gin.Trade-off between speed and noise margin.During pull-up, need: • high current for fast switching, • but also high resistance for high noise margin. ⇒ use current source as pull-up.6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-7 2. NMOS inverter with current-source pull-up I-V characteristics of current source: iSUP + 1 rISUP ociSUPvSUP _ 0 0 vSUP Equivalent circuit models: iSUP ISUPvSUP + _ rrococ large-signal model small-signal model • high current throughout voltage range: iSU P  ISU P • high small-signal resistance, roc.noise6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-8 NMOS inverter with current-source pull-up: load lineVDD iSUP=ID VGS=VDD iSUP ISUP VGS=VIN VIN VOUT CL VGS=VT 0 0 VDD VDS Transfer characteristics: VOUT VDD 0 0 VT VDD VIN High roc ⇒ high marginHighroc⇒high noise margin6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-9 Dynamics: VDD VDD iSUP iSUP VOUT: VOUT: HI LO LO HI VIN: CL VIN: CLLO HI HI LO pull-down pull-up Faster pull-up because capacitor charged at constant cur-rent. Faster pull-up because capacitor charged at constant cur-Fas rent.6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-10 2 PMOS as current-source pull-up I-V characteristics of PMOS: S G IDp D -IDp 0 VSGp VSGp=-VTp -IDp 0 saturation 0 VSDp 0 -VTp VSGp Note: enhancement-mode PMOS has VTp < 0. In saturation: −IDp ∝ (VSG + VTp)26.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-11 Circuit and load-line diagram of inverter with PMOS cur-rent source pull-up: VIN VB VOUT VDD CL VOUT VDD VIN 0 0 -IDp=IDn VDD PMOS load line for VSG=VDD-VB VOUT 0 VDD NMOS cutoff PMOS triode NMOS saturation PMOS triode NMOS saturation PMOS saturation NMOS triode PMOS saturation Transfer function: 0 VTn VDD VIN� � � � � � � 6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-12 Noise margin: • compute VM = VIN = VOU T • compute |Av(VM )| At VM Cox(VM − VTn)2 both transistors saturated: WnIDn = µn2Ln Wp−IDp = µpCox(VDD − VB + VTp)2 2Lp And: IDn = −IDp Then: � Wpµp LpVM = VTn + � Wn (VDD − VB + VTp) µn Ln6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-13 Small-signal equivalent circuit model at VM : G1 S1 D1 + -vin + -vgs1 + -voutgmnvgs1 ron G2 S2 D2 + -vsg2=0 gmpvsg2 rop + -vin + -voutgmnvin ron//rop Av = −gmn(ron//rop)6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-15 Screen shots of NMOS inverter transfer characteristics: 2 NMOS inverter with resistor pull-up 2 NMOS inverter with current source pull-up6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-14 NMOS inverter with current-source pull-up allows fast switching with high noise margins. But... when VIN = VDD, there is a direct current path between supply and ground ⇒ power consumption even if inverter is idling. VIN:HI VB VOUT:LO VDD CL VOUT VDD VIN 0 0 -IDp=IDn VDD PMOS load line for VSG=VDD-VB Would like to have current source that is itself switchable, i.e., it shuts off when input is high ⇒ CMOS!ower while in an6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-16 3. Complementary MOS (CMOS) Inverter Circuit schematic: VDD VIN VOUT CL Basic operation: •VIN =0 ⇒ VOUT = VDD VGSn =0 <VTn ⇒ NMOS OFFNMOS OFFVSGp = VDD > −VTp ⇒ PMOS ON •VIN = VDD ⇒ VOUT =0 VGSn = VDD >VTn ⇒ NMOS ON VSGp =0 < −VTp ⇒ PMOS OFFPMOS OFFNo p consumption idling y logic state.No power consumption while idling in any logic state.6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-17 Output characteristics of both transistors: IDn 0 VSDp -IDp VSGp VSGp=-VTp 0 0VDSn VGSn VGSn=VTn 0 Note: VIN = VGSn = VDD − VSGp ⇒ VSGp = VDD − VIN VOUT = VDSn = VDD − VSDp ⇒ VSDp = VDD − VOUT IDn = −IDp Combine into single diagram of ID vs. VOUT with VIN as parameter.VVail-to-rail” lo lo levels areound lo threshold od noise6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 13-18 VDD ID CL VIN VOUT VDD-VIN VIN 0 VOUT0  no current while idling in any logic state. Transfer function: NMOS cutoff PMOS triode VOUT VIN 0 0 VDDVTn VDD+VTp VDD NMOS saturation PMOS triode NMOS saturation PMOS saturation NMOS triode PMOS saturation NMOS triode PMOS cutoff  ”r gic: gic 0 and VDD  high |Av| ar gic ⇒ go margins ”rail-to-rail” logic: logic levels are 0andVDDhighh | Av| around logic thresholdd ⇒good noise margins6.012 - Microelectronic Devices and


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MIT 6 012 - lecture13annotat

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