6.012 Spring 2007 Lecture 12 1Lecture 12Digital Circuits (II)MOS INVERTER CIRCUITSOutline• NMOS inverter with resistor pull-up–The inverter• NMOS inverter with current-source pull-up• Complementary MOS (CMOS) inverter• Static analysis of CMOS inverterReading Assignment:Howe and Sodini; Chapter 5, Section 5.46.012 Spring 2007 Lecture 12 21. NMOS inverter with resistor pull-up: Dynamics•CLpull-down limited by current through transistor– [shall study this issue in detail with CMOS]•CLpull-up limited by resistor (tPLH≈ RCL)• Pull-up slowestVIN:LO HIVIN:HI LOVOUT:HI LOVOUT:LO HIVDDCLRVDDCLRpull-downpull-up6.012 Spring 2007 Lecture 12 31. NMOS inverter with resistor pull-up: Inverter design issues•R ↑⇒|RCL| ↑⇒ slow switching•gm↑⇒|W| ↑⇒ big transistor– (slow switching at input)Noise margins ↑⇒|Av| ↑⇒Trade-off between speed and noise margin.During pull-up we need:• High current for fast switching• But also high incremental resistance for high noise margin.⇒ use current source as pull-up6.012 Spring 2007 Lecture 12 42. NMOS inverter with current-source pull-up• High current throughout voltage range vSUP> 0 •iSUP= 0 for vSUP≤ 0 •iSUP= ISUP+ vSUP/ roc for vSUP> 0 • High small-signal resistance roc.Equivalent circuit models :I—V characteristics of current source:iSUPISUPvSUP1rocvSUPiSUP+_ISUProciSUPvSUP+_roclarge-signal model small-signal model6.012 Spring 2007 Lecture 12 5NMOS inverter with current-source pull-upStatic CharacteristicsInverter characteristics :High roc⇒ high noise marginsVINVOUTVDDCLiSUPiDvOUT = vDSVIN = VGS VDDISUP +VDDrocVOUTVIN12341234(a)(b)6.012 Spring 2007 Lecture 12 6PMOS as current-source pull-upNote: enhancement-mode PMOS has VTp<0.In saturation:I—V characteristics of PMOS:−IDp∝ VSG+ VTp()25 VSDGVGB−ID(VSG,VSD)(a) 123450100150200250300−IDp(µA) VSD (V) VSG = 3.5 V VSG = 0, 0.5, 1 V(cutoff region) VSG = 3 V VSG = 25 VSG = 2 V VSG = 1.5 V (b)VSD = VSG + VTp = VSG − 1 V (trioderegion)(saturation region)−IDp VD+_VSG+_VSD5+−+−+−6.012 Spring 2007 Lecture 12 7PMOS as current-source pull-up:Circuit and load-line diagram of inverter with PMOS current source pull-up:Inverter characteristics:VOUTVIN00VDDVTnVDDNMOS cutoffPMOS triodeNMOS saturationPMOS triodeNMOS saturationPMOS saturationNMOS triodePMOS saturationVOUTVDDVIN00-IDp=IDnVDDPMOS load line for VSG=VDD-VBVINVBVOUTVDDCL6.012 Spring 2007 Lecture 12 8PMOS as current-source pull-up:NMOS inverter with current-source pull-up allows high noise margin with fast switching• High Incremental resistance• Constant charging current of load capacitanceBut…When VIN= VDD, there is a direct current path between supply and ground⇒ power is consumed even if the inverter is idle.Ideally, we would like to have a current source that is itself switchable, i.e it shuts off when input is high⇒ CMOS!VIN:HIVBVOUT:LOVDDCLVOUTVDDVIN00-IDp=IDnVDDPMOS load line for VSG=VDD-VB6.012 Spring 2007 Lecture 12 93. Complementary MOS (CMOS) Inverter•VIN= 0 ⇒ VOUT= VDDVGSn= 0 < VTn⇒ NMOS OFFVSGp= VDD> - VTp⇒ PMOS ON•VIN= VDD⇒ VOUT= 0VGSn= VDD> VTn⇒ NMOS ONVSGp= 0 < - VTp⇒ PMOS OFFCircuit schematic:No power consumption while idle in any logic state!Basic Operation:VINVOUTVDDCL6.012 Spring 2007 Lecture 12 10Note:VIN= VGSn= VDD-VSGp⇒ VSGp=VDD-VINVOUT= VDSn= VDD-VSDp⇒ VSDp=VDD-VOUTIDn= -IDpCombine into single diagram of IDvs. VOUTwith VINas parameterVINVOUT1345IDn = −IDp−IDp = IDn(a)VDDVOUTVDDVOUTVIN(b)n-channelp-channel1 234512435VDDVDD2Output characteristics of both transistors:CMOS Inverter (Contd.):6.012 Spring 2007 Lecture 12 11CMOS Inverter (Contd.): • No current while idle in any logic stateInverter Characteristics:• “rail-to-rail” logic: logic levels are 0 and VDD• High |Av| around logic threshold ⇒good noise marginsVOUTVIN00VDD-VINIDVOUTVIN00VDDVTnVDD+VTpVDDNMOS cutoffPMOS triodeNMOS saturationPMOS triodeNMOS saturationPMOS saturationNMOS triodePMOS saturationNMOS triodePMOS cutoff6.012 Spring 2007 Lecture 12 122. CMOS inverter: noise margins• Calculate VM• Calculate Av(VM)• Calculate NMLand NMHCalculate VM(VM= VIN= VOUT)At VMboth transistors are saturated:IDn=Wn2LnµnCoxVM− VTn()2−IDp=Wp2LpµpCoxVDD− VM+ VTp()2VOUTVIN00VDDVMVILVIHVMVDDAv(VM)NMLNMH6.012 Spring 2007 Lecture 12 13CMOS inverter: noise margins (contd.)Since :Define:kn=WnLnµnCox; kp=WpLpµpCoxIDn=−IDpThen:12knVM− VTn()2=12kpVDD− VM+ VTp()2Solve for VM:VM=VTn+kpknVDD+ VTp()1+kpknUsually, VTnand VTpfixed and VTn= - VTp⇒ VMengineered through kp/knratio.6.012 Spring 2007 Lecture 12 14CMOS inverter: noise margins (contd..)• Symmetric case: kn= kpVM=VDD2This implies:kpkn=1 =WpLpµpCoxWnLnµnCox≈WpLpµpWnLn2µp⇒WpLp≈ 2WnLnSince usually Lp≈ Ln = Lmin⇒ Wp≈ 2Wn• Asymmetric case:kn>> kp, orWnLn>>WpLpVM≈VTnNMOS turns on as soon as VINgoes above VTn.• Asymmetric case:kn<< kp, orWnLn<<WpLpVM≈VDD+VTpPMOS turns on as soon as VINgoes below VDD+ VTp.6.012 Spring 2007 Lecture 12 15CMOS inverter: noise margins (contd…)Calculate Av(VM)• Small signal model:Av=− gmn+ gmp()ron// rop()This can be rather large.G1G1=G2S1S1=S2D1D1=D2+-vin+-vgs1+-voutgmnvgs1ron+-vin+-voutgmnvingmpvinron//ropG2S2D2+-vsg2=-vingmpvsg2rop6.012 Spring 2007 Lecture 12 16CMOS inverter: calculate noise margins (contd.)• Noise-margin low, NML:VIL= VM−VDD−VMAvNML= VIL− VOL= VIL= VM−VDD− VMAvVOUTVIN00VDDVMVILVIHVMVDDAv(VM)NMLNMH• Noise-margin high, NMH:VIH= VM1 +1Av⎛ ⎝ ⎜ ⎞ ⎠ ⎟ NMH= VOH− VIH= VDD− VM1+1Av⎛ ⎝ ⎜ ⎞ ⎠ ⎟6.012 Spring 2007 Lecture 12 17What did we learn today?• In NMOS inverter with resistor pull-up, there is a trade-off between noise margin and speed• Trade-off resolved using current source pull-up– Use PMOS as current source.• In NMOS inverter with current-source pull-up: if VIN= High, there is power consumption even if inverter is idling.• Complementary MOS: NMOS and PMOS switch-on alternatively.– No current path between power supply and ground– No power consumption while idling• Calculation of CMOS–VM– Noise MarginSummary of Key
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