6.012 - Microelectronic Devices and Circuits Lecture 19 - Differential Amplifier Stages - Outline Announcements Design Problem - coming out tomorrow; PS #10 looks at pieces; neglect the Early effect in large signal analyses Review - Single-transistor building block stages Common source: general purpose gain stage, workhorse Common gate: small Rin, large Rout, unity Ai, same A as CSv Source follower: large Rin, small Rout, unity Av, same Ai as CS Series and Shunt feedback: we'll see in special situations Differential Amplifier Stages - Large signal behavior General features: symmetry, inputs, outputs, biasing (Symmetry is the key!) Large signal transfer characteristic Difference- and common-mode signalsDecomposing and reconstructing general signals Half-circuit incremental analysis techniquesLinear equivalent half-circuits Difference- and common-mode analysisExample: analysis of source-coupled pair Clif Fonstad, 11/17/09 Lecture 19 - Slide 1IBIAS-V+V123IBIAS-V+V123Linear amplifier layouts: The practical ways of puttinginputs to, and taking outputs from, transistors to form linear amplifiers There are 12 choices: three possible nodes to connect to the input, and for each one, two nodes from which to take an output, and two choices of what to do with the remaining node (ground it or connect it to something). Not all these choices work well, however. In fact only three do: Name Input Output Grounded Common source/emitter 1 2 3 Common gate/base 3 2 1 Common drain/collector 1 3 2 (Source/emitter follower) Source/emitter degeneration 1 2 none Clif Fonstad, 11/17/09 Lecture 19 - Slide 2IBIASV-V+vout+-vin+-CECOIBIASV-V+vout+-vIN+-COCI • Three MOSFET single-transistor amplifiers V+ + IBIAS COvin -+ vout -V-SOURCE FOLLOWER Input: gate Output: source Common: drain Substrate: to source IBIASV-V+vin+-CECOvout+-COMMON SOURCE Input: gate Output: drain Common: source Substrate: to source IBIASV-V+vout+-vIN+-COCICOMMON GATE Input: source; Output: drain Common: gate Substrate: to ground vout + -vin + -vout + -vin + -vout + -vin + -Clif Fonstad, 11/17/09 Lecture 19 - Slide 3• Single-transistor amplifiers with feedbackV+ + vin + CO V+ RF CO + voutvout + --vin --RF IBIASIBIAS CE CE V-V-SERIES FEEDBACK PARALLEL FEEDBACK* vout+-vin+-RFClif Fonstad, 11/17/09 vout+-vin+-RF* Also termed "source degeneracy" Lecture 19 - Slide 4• Summary of the single transistor stages (MOSFET) ! MOSFETVoltagegain, AvCurrentgain, AiInputresistance, RiOutputresistance, RoCommon source "gmgo+ gl[ ]= "gmrl'( )# # ro=1go$ % & ' ( ) Common gate * gm+ gmb[ ]rl'*1 *1gm+ gmb[ ]* ro1+gm+ gmb+ go[ ]gt+ , - . / 0 Source followergm[ ]gm+ gmb+ go+ gl[ ]*1 # #1gm+ go+ gl[ ]*1gmSource degeneracy(series feedback)* "rlRF# # * roShunt feedback "gm" GF[ ]go+ GF[ ]* "gmRF"glGF1GF1" Av[ ]ro|| RF=1go+ GF[ ]$ % & ' ( ) ! Power gain, Ap= Av" AiNote: When vbs = 0 the gmb factors should be deleted. Clif Fonstad, 11/17/09 Lecture 19 - Slide 5• Summary of the single transistor stages (bipolar) ! BIPOLARVoltagegain, AvCurrentgain, AiInputresistance, RiOutputresistance, RoCommon emitter "gmgo+ gl[ ]="gmrl'( )"#glgo+ gl[ ]r$ro=1go% & ' ( ) * Common basegmgo+ gl[ ]= gmrl'( )+1 +r$#+1[ ]+#+1[ ]roEmitter followergm+ g$[ ]gm+ g$+ go+ gl[ ]+1#glgo+ gl[ ]+#r$+#+1[ ]rl'rt+ r$#+1[ ]Emitter degeneracy + "rlRF+#+ r$+#+1[ ]RF+ roShunt feedback "gm" GF[ ]go+GF[ ]+ "gmRF"glGF1g$+GF1" Av[ ]ro|| RF=1go+GF% & ' ( ) * ! Power gain, Ap= Av" AiClif Fonstad, 11/17/09 Lecture 19 - Slide 6-- Differential Amplifiers: emitter- and source-coupled pairs V+ ++ vOUT1 vOUT2 V+ vOUT1 + -vOUT2 + -IBIAS V-++ ++ vIN2vIN1 vIN2 vIN1 ----IBIAS V-Emitter-coupled pair Source-coupled pair Why do we care? - They amplify only difference-mode signals They are easy to interconnect and cascade They help us eliminate coupling capacitors They are optimally suited to integration Clif Fonstad, 11/17/09 Lecture 19 - Slide 7IBIASvI1vO1+-vO2+-+-vI2+-+-vO-VSS+VDDRDRDM1M2Differential Amplifiers: large signal analysis of source coupled pairs Source-coupled pair Below: Schematic with resistor loads Right: Large signal equiv. circuit in saturation Analysis: vI1 - vGS1 +vGS2 - vI2 = 0, vO1 = VDD - RDiD1, vO2 = VDD - RDiD2 KCL at one node: iD1 + iD2 = IBIAS MOSFET relationships: iD1 = K(vGS1-VT)2/2; iD2 = K(vGS2-VT)2/2 (see text for details of analysis) Clif Fonstad, 11/17/09 Lecture 19 - Slide 8 3 KVL loops:Diff. Amps: large signal analysis of source coupled pairs, cont. Results: The outputs again only depend on the difference between the two inputs, (vI1 - vI2): Slope around origin = -gmRD ! vO1= VDD"RD2K vIN1" vIN 2[ ]2+ IBIAS +K2vIN1" vIN 2[ ]4IBIASK" vIN1" vIN 2[ ]2# $ % & % ' ( % ) % vO2= VDD"RD2K vIN1" vIN 2[ ]2+ IBIAS "K2vIN1" vIN 2[ ]4IBIASK" vIN1" vIN 2[ ]2# $ % & % ' ( % ) % vO= "RDK2vIN1" vIN 2[ ]4IBIASK" vIN1" vIN 2[ ]2Symmetrical vo Clif Fonstad, 11/17/09 Only the difference in the inputs matters!! Lecture 19 - Slide 9IBIAS+VCCvI1+-vO1+-vO2+-vI2+--VEE+-vORCRCQ2Q1 Differential Amplifiers: large signal analysis ofemitter coupled pairs Emitter-coupled pair Below: Schematic with resistor loads Right: Large signal equivalent circuit in FAR Analysis: 3 KVL loops: vI1 - vBE1 +vBE2 - vI2 = 0, vO1 = VCC - RCαFiF1, vO2 = VCC - RCαFiF2 KCL at one node: iF1 + iF2 = IBIAS Ideal diode relationships: iF1 ≈ IES exp (qvBE1/kT), iF2 ≈ IES exp (qvBE2/kT) (see text for details of analysis) Clif Fonstad, 11/17/09 Lecture 19 - Slide 10Diff. Amps: large signal analysis of emitter coupled pairs, cont. Results: The outputs only depend on the difference between the inputs, (vI1 - vI2): Slope around origin = -gmRC ! vO1=VCC"#FRCIBIAS1+e"q vI1"vI 2( )kT[ ]vO2=VCC"#FRCIBIAS1+eq vI1"vI 2( )kT[ ]vO="#FRCIBIAStanhq vI1" vI 2( )2kTSymmetrical Clif Fonstad, 11/17/09 Only the difference in the inputs matters!! Lecture 19 - Slide 11_______________________________________ Differential Amplifier Analysis - difference-mode and common-mode signals Any pair of signals can be decomposed into a portion that is the identical in both, and a portion that is equal, but opposite in both. For example, if we have two voltages, v1 and v2, we can define a common-mode signal, vC, and a difference-mode signal, vD, as: vC= (v1+ v2)/2 vD= v1-
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