6.012 - Microelectronic Devices and Circuits Lecture 16 - CMOS scaling; The Roadmap - Outline • Announcements PS #9 - Will be due next week Friday; no recitation tomorrow. Postings - CMOS scaling (multiple items) Exam Two - Tonight, Nov. 5, 7:30-9:30 pm • Review - CMOS gate delay and power Lecture 15 results: Gate Delay = 12 n Lmin 2 VDD/ µn(VDD - VT)2 Pdyn@fmax ∝ CLVDD 2/GD = KnVDD (VDD - VT)2/4 Velocity Saturation • CMOS scaling rules Power density issues and challenges Approaches to a solution: Dimension scaling alone Scaling voltages as well • The Road Map; the Future Size and performance evolution with time How long can it go on? Clif Fonstad, 11/5/09 Lecture 16 - Slide 1CMOS: transfer characteristic Complete characteristic w.o. Early effect: VDDvOUTvIN++–– KpVTp KnVTnVTnVDDVDD-VTpVDD/2VINVOUT(VDD+ VTp)(VDD/2-VTp)(VDD/2-VTn)VDD/2NOTE: We design CMOS inverters to have Kn = Kp and VTn = -VTp to obtain the optimum symmetrical characteristic. Clif Fonstad, 11/5/09 Lecture 16 - Slide 2CMOS: transfer characteristic calculation, cont. We found from an LEC analysis that the slope in Region III is not infinite, but is instead: Lecture 16 - Slide 3 VDDVDDVDD/2vINvOUTVDD/2AvVTnVDDVDD-VTpVDD/2vINvOUT(VDD- |VTp|)VDD/2Av! Av"voutvin=#vOUT#vINQ =VDD/2,VDD/2( )= $gmn+ gmp[ ]gon+ gop[ ]= $2 2Kn%n+%p[ ]IDnQuick approximation: An easy way to sketch the transfer characteristic of a CMOS gate is to simply draw the three straight line portions in Regions I, III, and V: Clif Fonstad, 11/5/09CMOS: switching speed; minimum cycle time The load capacitance: CL • Assume to be linear • Is proportional to MOSFET gate area • In channel: µe= 2µh so to have Kn = Kp we must have Wp/Lp = 2Wn/Ln Typically Ln = Lp = Lmin and Wn = Wmin, so we also have Wp = 2Wmin ! CL" n WnLn+ WpLp[ ]Cox*= n WminLmin+ 2WminLmin[ ]Cox*= 3nWminLminCox*Charging cycle: vIN: HI to LO; Qn off, Qp on; vOUT: LO to HI • Assume charged by constant iD,sat VDDvOUTvIN++––CLQpQnClif Fonstad, 11/5/09 Lecture 16 - Slide 4 ! iCh arge= "iDp#Kp2VDD" VTp[ ]2=Kn2VDD" VTn[ ]2qCh arge= CLVDD$Ch arge=qCh argeiCh arge=2CLVDDKnVDD" VTn[ ]2 =6nWminLminCox*VDDWminLminµeCox*VDD" VTn[ ]2=6nLmin2VDDµeVDD" VTn[ ]2CMOS: switching speed; minimum cycle time, cont. Discharging cycle: vIN: LO to HI; Qn on, Qp off; vOUT: HI to LO • Assume discharged by constant iD,sat VDDvOUTvIN++––CLQpQn! iDisch arge= iDn"Kn2VDD# VTn[ ]2qDisch arge= CLVDD$Disch arge=qDisch argeiDisch arge=2CLVDDKnVDD# VTn[ ]2 =6nWminLminCox*VDDWminLminµeCox*VDD# VTn[ ]2=6nLmin2VDDµeVDD# VTn[ ]2Minimum cycle time: vIN: LO to HI to LO; vOUT: HI to LO to HI ! "Min.Cycle="Ch arge+"Disch arge=12nLmin2VDDµeVDD# VTn[ ]2Clif Fonstad, 11/5/09 Lecture 16 - Slide 5CMOS: switching speed; minimum cycle time, cont. Discharging and Charging times: What do the expressions tell us? We have ! "MinCycle=12nLmin2VDDµeVDD# VTn[ ]2This can be written as: ! "MinCycle=12nVDDVDD# VTn( )$LminµeVDD# VTn( )LminThe last term is the channel transit time: ! LminµeVDD" VTn( )Lmin=Lminµe#Ch=Lmins e,Ch=$ChTransitThus the gate delay is a multiple of the channel transit time: ! "MinCycle=12nVDDVDD# VTn( )"ChannelTransit= n'"ChannelTransitClif Fonstad, 11/5/09 Lecture 16 - Slide 6CMOS: power dissipation - total and per unit area Average power dissipation Only dynamic for now ! Pdyn,ave= EDissipated per cyclef = CLVDD2= 3nWminLminCox*VDD2fPower at maximum data rate Maximum f will be 1/τGate Delay Min. ! Pdyn@ fmax=3nWminLminCox*VDD2"Min.Cycle= 3nWminLminCox*VDD2#µeVDD$ VTn[ ]212nLmin2VDD =14WminLminµeCox*VDDVDD$ VTn[ ]2Power density at maximum data rate Assume that the area per inverter is proportional to WminLmin ! PDdyn@ fmax=Pdyn@fmaxInverterArea"Pdyn@fmaxWminLmin=µeCox*VDDVDD# VTn[ ]2Lmin2Clif Fonstad, 11/5/09 Lecture 16 - Slide 7CMOS: design for high speed Maximum data rate Proportional to 1/τMin Cycle ! "Min.Cycle="Ch arge+"Disch arge=12nLmin2VDDµeVDD# VTn[ ]2Implies we should reduce Lmin and increase VDD. Note: As we reduce Lmin we must also reduce tox, but tox doesn't enter directly in fmax so it doesn't impact us here Power density at maximum data rate Assume that the area per inverter is proportional to WminLmin ! PDdyn@ fmax"Pdyn@fmaxWminLmin=µe#oxVDDVDD$ VTn[ ]2toxLmin2Shows us that PD increases very quickly as we reduce Lmin unless we also reduce VDD (which will also reduce fmax). Note: Now tox does appear in the expression, so the rate of increase with decreasing Lmin is even greater because tox must be reduced along with L to stay in the gradual channel regime. How do we make fmax larger without melting the silicon? Clif Fonstad, 11/5/09 By following CMOS scaling rules, the topic of today's lecture. Lecture 16 - Slide 8CMOS: velocity saturation Sanity check before looking at device scaling CMOS gate lengths are now under 0.1 µm (100 nm). The electric field in the channel can be very high: Ey ≥ 104 V/cm when vDS ≥ 0.1 V. Model A Electrons: Holes: Clearly the velocity of the electrons and holes in the channel will be saturated at even low values of vDS! What does this mean for the device and inverter characteristics? Clif Fonstad, 11/5/09 Lecture 16 - Slide 10MOS: Output family with velocity saturation iD vDS EcritL ! iD(vGS,vDS,vBS) "0 for vGS< VT, 0 < vDSW ssatCox*vGS#VT(vBS)[ ]for VT< vGS, $critL < vDSWLµeCox*vGS#VT(vBS)[ ]vDSfor VT< vGS, 0 < vDS< $critL% & ' ' ( ' ' Cutoff Saturation Linear This simple model for the output characteristics of a very short channel MOSFET (plotted above) provides us an easy way to understand the impact of velocity saturation on MOSFET and CMOS inverter performance. Clif Fonstad, 11/5/09 Lecture 16 - Slide 11CMOS: Gate delay and fmax with velocity saturation Charge/discharge cycle and gate delay: The charge and discharge currents, charges, and times are now: ! iDisch arge= iCh arge= WminssatCox*VDD" VTn( )qDisch arge= qCh arge= CLVDD= 3WminLminCox*VDD#Disch arge=#Ch arge=qDisch argeiDisch arge=3WminLminCox*VDDWminssatCox*VDD" VTn( )=3nLminVDDssatVDD" VTn( )CMOS minimum cycle time and power density at fmax: ! "Min.Cycle#LminVDDssatVDD$ VTn[ ]= n'"ChanTransit! "Min.Cycle="Ch arge+"Disch arge=6n LminVDDssatVDD# VTn[ ]! "ChanTransit=LssatNote: Lessons: We still benefit from reducing L, but not as quickly.Channel transit time, Lmin/ssat, is still critical. Clif Fonstad, 11/5/09 Lecture 16 - Slide 12CMOS: Power and power density with velocity saturation Average power dissipation
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