6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 7-1 Lecture 7 - PN Junction and MOS Electrostatics (IV) Electrostatics of Metal-Oxide-Semiconductor Structure September 29, 2005 Contents: 1. Introduction to MOS structure 2. Electrostatics of MOS at zero bias 3. Electrostatics of MOS under bias Reading assignment: Howe and Sodini, Ch. 3, §§3.7-3.86.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 7-2 Key questions • What is the big deal about the metal-oxide-semiconductor structure? • What do the electrostatics of the MOS structure look like at zero bias? • How do the electrostatics of the MOS structure get modified if a voltage is applied across its terminals?6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 7-31. IntroductionMetal-Oxide-Semiconductor structure:metal interconnect to bulkmetalinterconnect to gaten+ polysilicon gategate oxide εox= 3.9 εop-typeεs= 11.7 εox0MOS at the heart of the electronics revolution:• Digital and analog functions: Metal-Oxide-SemiconductorField-Effect Transistor (MOSFET) is key element ofComplementary Metal-Oxide-Semiconductor (CMOS)circuit family• Memory function: Dynamic Random Access Mem-ory (DRAM) and Flash Erasable Programmable Mem-ory (EPROM)• Imaging: Charge-Couple Device (CCD) camera• Displays: Active-Matrix Liquid-Crystal Displays• ...(MOSFET)(CMOS)(DRAM)(EPROM)6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 7-4 2. MOS electrostatics at zero bias Idealized 1D structure: "metal" (n+ polySi) oxide semiconductor (p type) contactcontact x0-tox • Metal: does not tolerate volume charge ⇒ charge can only exist at its surface • Oxide: insulator ⇒ no volume charge (no free carriers, no dopants) • Semiconductor: can have volume charge (SCR) semiconductor. Thermal equilibrium can’t be established through oxide; need wire to allow transfer of charge between metal and MOS structure: sandwich of dissimilar materials ⇒ car-rier transfer ⇒ space-charge region at zero bias ⇒ built-in potential6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 7-5 For most metals on p-Si, equilibrium achieved by elec-trons diffusing from metal to semiconductor and holes from semiconductor to metal: log po, no Na po no ni2 Na x-tox 0 xdo 2Remember: nopo = ni Fewer holes near Si/SiO2 interface ⇒ ionized acceptors exposed (volume space charge)oximation6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 7-6 2 Space charge density x ρο 0 xdo -qNa 0 -tox log po, no po no Na ni2 Na x0-tox xdo QG • In semiconductor: space-charge region close to Si/SiO2 interface ⇒ can do depletion apprdepletion approximation• In metal: sheet of charge at metal/SiO2 interface • Overall charge neutrality x ≤−tox ρo(x)= QG δ(−tox) −tox <x < 0 ρo(x)=0 0 < x<xdo ρo(x)= −qNa xdo <x ρo(x)= 0 � 6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 7-7 2 Electric field Integrate Gauss’ equation: 1 Eo(x2) − Eo(x1)= xx12 ρo(x)dx At interface between oxide and semiconductor: change in permittivity ⇒ change in electric field oxEox = sEs Eox s = 3 Es ox Eox 0 E Es x06.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 7-8 Start integrating from deep inside semiconductor: Eox x 0 xdo Eο 0 Es -tox x ρο 0 xdo -qNa 0 -tox xdo <x Eo(x)= 0 0 < x<xdo Eo(x)= −qNa s (x − xdo) −tox <x < 0 Eo(x)= s ox Eo(x =0+)= qNaxdo ox x< −tox Eo(x)= 06.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 7-9 2 Electrostatic potential (with φ =0 @ no = po = ni) kTno kTpoφ = ln φ = − ln q ni q ni In QNR’s, no and po known ⇒ can determine φ: in n+ gate: no = N + ⇒ φg = φn+d in p-QNR: po = Na ⇒ φp = −kT ln Na q ni x φο φn+ φB 0 xdo0 -tox φp Built-in potential: kT NaφB = φg − φp = φn+ + ln q ni� 6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 7-10 To get φo(x), integrate Eo(x); start from deep inside semi-conductor bulk: φo(x2) − φo(x1)= − xx12 Eo(x)dx Eox x 0 xdo Eο 0 Es -tox x φο φB φn+ 0 xdo 0 -tox φp Vox,o VB,o xdo<x φo(x)= φp qNa 0 < x<xd φo(x)= φp + (x − xdo)2 2 s qNax2 do qNaxdo−tox <x < 0 φo(x)= φp + + (−x)2 s ox x< −tox φo(x)= φn+� � � � � � � � � 6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 7-11 2 Still don’t know xdo ⇒ need one more equation: Potential difference across structure has to add up to φB : qNax2 do qNaxdotoxφB = VB,o + Vox,o = + 2 s ox Solve quadratic equation: � 2 2 � s � oxφB s � 4φB xdo = tox[� 1+ − 1] = [� 1+ − 1] ox sqNat2 γ2 ox Cox where Cox is capacitance per unit area of oxide [units: F/cm2]: oxCox = tox and γ is body factor coefficient [units: V −1/2]: 1 γ = 2 sqNaCox6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 7-12 2 Numerical example: −3Nd =1020 cm−3,Na =1017 cm ,tox =8 nm φB = 550 mV + 420 mV = 970 mV Cox =4.3 × 10−7 F/cm2 γ =0.43 V 1/2 xdo =91 nm6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 7-13 There are also contact potentials ⇒ total contact-to-contact potential difference is zero! "metal" oxide semiconductor (p type) contactcontact x φο φB φn+ 0 xdo0 -tox φp6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 7-14 3. MOS electrostatics under bias Apply voltage to gate with respect to semiconductor: x0-tox "metal" (n+ polySi) oxide semiconductor (p type) contactcontact VGB + -Electrostatics of MOS structure affected ⇒ potential dif-ference across entire structure now =0. How is potential difference accommodated? Potential can drop in: • gate contact • n+-polysilicon gate • oxide • semiconductor SCR • semiconductor QNR • semiconductor contact6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 7-15 Potential difference shows up across oxide and SCR in semiconductor: x φ φB 0 xdo0 -tox φB+VGB ? VGB Oxide is insulator ⇒ no current anywhere in structure In SCR, quasi-equilibrium situation prevails ⇒ new balance between drift and diffusion • electrostatics qualitatively identical to zero bias (but amount of charge redistribution is different) 2• np = n i6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 7-16 Apply VGB > 0: potential difference across structure in-creases ⇒ need larger charge
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