1Copyright 2001, Regents of University of CaliforniaLecture 1: 01/22/03 A.R. NeureutherVersion Date 01/21/03EECS 42 Intro. electronics for CS Spring 2003EECS 42 Introduction to Electronics for Computer ScienceAndrew R. NeureutherMW 3-4, 10 EvansPlus Discussion Sectionhttp://inst.EECS.Berkeley.EDU/~ee42/Copyright 2001, Regents of University of CaliforniaLecture 1: 01/22/03 A.R. NeureutherVersion Date 01/21/03EECS 42 Intro. electronics for CS Spring 2003EECS 42Course OverviewSome questions will this course may answer: How do electronic circuits work (e.g. how do they amplify, how do they represent 1’s and 0’s, how do they perform logic) ? What determines performance (e.g. why is the Intel P4 so slow and a power hog, and how will they fix it) ? Why is CMOS dominant and why will it continue it’s dominance (e.g. versus bipolar or new technologies)? What does CMOS look like (under the microscope) ? What is the future prognosis for performance of computers ? Why are analog circuits so important in this digital world ?2Copyright 2001, Regents of University of CaliforniaLecture 1: 01/22/03 A.R. NeureutherVersion Date 01/21/03EECS 42 Intro. electronics for CS Spring 2003Goals of EECS 42•Provide an overview of electronics– Terminology– Organization of the field•Provide career foundation cornerstones – Skills – circuit analysis– Performance estimates – what sets fundamental limits– Examples of modern and changing technologyCopyright 2001, Regents of University of CaliforniaLecture 1: 01/22/03 A.R. NeureutherVersion Date 01/21/03EECS 42 Intro. electronics for CS Spring 2003Course OverviewEECS 42 – Electronics for Computer ScienceR Introduces “hardware” side of EECSCourse content : (Not precisely in this order)R Basic Device and Circuit IdeasR Digital Circuits and Logic DelaysR Physical realization/CMOSR Performance limits of CMOS digital circuits3Copyright 2001, Regents of University of CaliforniaLecture 1: 01/22/03 A.R. NeureutherVersion Date 01/21/03EECS 42 Intro. electronics for CS Spring 2003RVoutVCo0=+−5VRC1µsec=CPULSE: Output is Rising exponential then Falling exponentialExample: Switch rises at t =0, falls at t = 0.1, 1 or 10µsec (Do 1µsec case)Solution: for RC = 1µsec: during the first rise V obeys:0123456012345time (microseconds)Vout610te1[5V−−−=]Now starting at 1µsec we aredischarging the capacitor so the form is a falling exponential withinitial value 3.16 V:Thus at t = 1µsec, rising voltage reaches]e1[5=−-13.16VWhat is equation?Lecture 7Copyright 2001, Regents of University of CaliforniaLecture 1: 01/22/03 A.R. NeureutherVersion Date 01/21/03EECS 42 Intro. electronics for CS Spring 2003EXAMPLE WITH BOTH SPECIAL CASES+_I1R4R1R2R3V2abcd()0423211=+−+−−RVVRRVRVIaaaLecture 84Copyright 2001, Regents of University of CaliforniaLecture 1: 01/22/03 A.R. NeureutherVersion Date 01/21/03EECS 42 Intro. electronics for CS Spring 2003C,B,AD)BA( +)(__CB⋅BDtttttLogic stateτττ2τ2τ03ττTIMING DIAGRAMSShow transitions of variables vs timeABCNote that becomes valid two gate delays after B&C switch, because the invert function takes one delay and the NAND function a second.)(__CB⋅No change at t = 3τNote becomes valid one gate delay after B switchesB10Lecture 11Copyright 2001, Regents of University of CaliforniaLecture 1: 01/22/03 A.R. NeureutherVersion Date 01/21/03EECS 42 Intro. electronics for CS Spring 2003CASCADE OP-AMP CIRCUITSV1+−V3V2RFR1R2R3V0+−1K9KIINHow do you get started on finding VO?Hint: IINdoes not affect VO1See the further examples of op-amp circuits in the readerHint: Identify StagesLecture 145Copyright 2001, Regents of University of CaliforniaLecture 1: 01/22/03 A.R. NeureutherVersion Date 01/21/03EECS 42 Intro. electronics for CS Spring 2003Composite Current Plot for the 42PDCircuit with 200kΩLoad to GroundState 1VOUT(V)035IOUT(µA)2060100State 3State 5VTHEVENIN (Open Load)INORTON (Open Load)VTHEVENIN (200KΩ Load) = 3. 3 VINORTON (200KΩ Load)VOUTIOUTOutputVINVDDRPULL UPRLOAD(200KΩ)Lecture 15Copyright 2001, Regents of University of CaliforniaLecture 1: 01/22/03 A.R. NeureutherVersion Date 01/21/03EECS 42 Intro. electronics for CS Spring 2003Logic Gate Propagation Delay (Cont.)At t=0, B and C switch to high = VDD and A remains low.ABCABCVDDVOUTRURURURDRDRDCOUT= 50 fFCOUTdischarges through the pull-down resistance of gates B and C in series.∆t = 0.69(RDB+RDC)COUT= 0.69(20kΩ)(50fF) = 690 psThe propagation delay is two times longer than that for the inverter!Lecture 176Copyright 2001, Regents of University of CaliforniaLecture 1: 01/22/03 A.R. NeureutherVersion Date 01/21/03EECS 42 Intro. electronics for CS Spring 2003Combinatorial Logic and Clocked Latches: Signal FlowA1B1C1A1C1B1VDDVOUT-C1A2B2A2VDDVOUT-C2VDDVOUT-L1VDDVMID-L1 φφφφCL1CL2VIN-L1VDDVOUT-L2VDDVMID-L2 φφφφCL1CL2VIN-L2VDDVOUT-L0VDDVMID-L0 φφφφCL1CL2VIN-L0B2=0Latch 0Latch 2Latch 1Logic 1Logic 2B2A1 =1, C1 =0φ
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