Lecture 13Today we will Examine how the logic gate model (RC circuit) reacts to a sequence of input changes Relate these results to clocking speed Define propagation delay Introduce digital logic gates Examine how signals propagate through logic circuitstimeVin0timeVin0VouttimeVin0VoutSequential Switching What if we step up the input to a logic circuit, wait for the output to respond, then bring the input back down to perform the next computation?We need to wait for the output to reach a recognizable logic level, before changing the input again.This affects clock speed.0123456012345Time01234560 5 10 15 20 25TimeVin, VoutPulse DistortionPulse width = 10RCPulse width = RC+Vout(t)–RVin(t)+−CVin, VoutExample Suppose that the capacitor is discharged at t=0. With Vin(t) as shown, find Vout(t).+Vout(t)–Vin(t)+−1 nF2.5 kΩΩΩΩ4 V5 µµµµsVin(t)tExample First, Vout(t) will approach 4 V exponentially. We write the equation for this part using: Initial condition Vout(0) = 0 V Final value Vout,f= 4 V Time constant RC = (2.5 kΩ)(1 nF) = 2.5 µsVout(t) = Vout,f-(Vout(0)-Vout,f)e-t/RCVout(t) = 4-4e-t/2.5µsV for 0 ≤ t ≤ 5 µsExample Then, at 5 µs, Vout(t) will approach 0 V exponentially. We write the equation for this part using: Initial condition Vout(5 µs) = ? Use equation from previous step, since Voutis continuous.Vout(5µs) = 4-4e-5µs/2.5µs= 3.44 V Final value Vout,f= 0 V Time constant RC = (2.5 kΩ)(1 nF) = 2.5 µsVout(t) = Vout,f-(Vout(t0) -Vout,f)e-(t-t0)/RCVout(t) = 3.44e-(t-5µs)/2.5µsfor t > 5 µs00.511.522.533.540 2 4 6 8 10Vout(t) =4-4e-t/2.5µsfor 0 ≤ t ≤ 5 µs3.44e-(t-5µs)/2.5µsfor t > 5 µsExampleVin(t)Vout(t)t (µµµµs)Design Issues How long between successive inputs? Need output to reach recognizable logic level Output must be at this level long enough to serve as input to next logic gate How many consecutive logic gates does signal go through before being “cleaned up” or saved in static memory cell? Eventually the signal gets really bad But adding hardware adds cost and delayPropagation Delay Suppose an input goes from some initial voltage to some final voltage. In our examples, the input switch is immediate, but in practice it is not. Propagation delay is officially defined as:(time when output is halfway to final value) minus(time when input is halfway to final value) IllustrationUsing our equation for Vout(t), we can find:tP,HL(time when Vout(t) = 2 V, as it goes from 0 V to 4 V) – 0 stP,LH(time when Vout(t) = 1.72 V, as it goes from 3.44 V to 0 V) –5 µs00.511.522.533.540 2 4 6 8 10tP,HLtP,LHtP,HL= tP,LH= 1.725 µµµµsPropagation Delay It’s not a coincidence that the propagation delays were the same. For a general RC circuit that has an input voltage switch at t = t0,Vout(t) = Vout,f-(Vout(t0) -Vout,f)e-(t-t0)/RC The time when Vout(t) is ½ (Vout,f+ Vout(t0)) is given by½(Vout,f+ Vout(t0)) = Vout,f-(Vout(t0) -Vout,f)e-(t-t0)/RC Simplifying,½ = e-(t-t0)/RCt = (ln 2)(RC) + t0 The propagation delay, the difference between this time and t0, istP= (ln 2)(RC) Depends only on time constant!Graphing Propagation through Multiple Logic Gates We will want to examine how these RC-related delays affect a signal going through multiple logic gates. The math involved in putting an RC output (decaying exponential) into another RC circuit is not so easy. So, when analyzing a circuit with many logic gates, we will use the following simplification:Logic Gate0tVtPtV→→Logic Gates We have been using a simple RC circuit to model a logic gate. In each case, the final value of Voutwas Vin. This will not always be true; sometimes, the output will go to logic 0 when the input is logic 1 and vice-versa. To determine what the final value of a logic gate output will be, we need to learn the types of logic gates.Logic GatesABC=A·BANDC = ABNANDBA⋅NORABBA+AAORABC=A+B(EXCLUSIVE OR)ABBAC ⊕=NOTXORLogic Functions: Truth TablesWe specify what a logic circuit does by listing the output for each possible input. This listing is called a truth table.0110AANOT0111100110101000A·BA·BBAAND NANDLogic Functions: Truth Tables0111010101101000A+BA+BBAOR NOR1011010101101000A ∆ BA ∆BBAXOR XNORTiming Diagrams Now let’s look at how signals propagate through logic gates, taking delay into consideration. Sketch the output for each logic gate in a more complicated circuit.ABA(A)·Bt10A, Bt10AtPt10tP(A)·B2tPStrategy for Timing DiagramsTo find the output for a particular gate, Graph the inputs for that gate Graph the result of the logic gate using the input graphs Shift right by one tPExampleDABCt10A, B,
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