Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 18: 10/3/01 A.R. NeureutherVersion Date 10/30/01Lecture 18: October 31, 2001Logic Switched Resistor ModelA) Worst Case Input ScenarioB) Cascade Stages for Many InputsC)Typical 0.25 µm Device ParametersReading: lecture viewgraphsCopyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 18: 10/3/01 A.R. NeureutherVersion Date 10/30/01Transient Gate Problem: Discharging and Charging Capacitance on the OutputVOUTIOUTOutputVIN-DVDDVIN-Up-type MOSTransistor(PMOS)n-type MOSTransistor(NMOS)VIN= VDD= 5VCOUT= 50 fF5V => 0Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 18: 10/3/01 A.R. NeureutherVersion Date 10/30/01Output Capacitance Voltage vs. TimeWhen VOUT> VOUT-SAT-Dthe available current is IOUT-SAT-DVOUT(0) = 5VCOUT= 50 fFIOUT-SAT-D= 100 µAVOUT(V)035IOUT(µA)2060100VIN= 5VIOUT-SAT-D= 100 µAAssume that the necessary voltage swing to cause the next downstream gate to begin to switch is VDD/2 or 2.5V. The propagation delay is thusnsAVfFIVCIVCtDSATOUTDDOUTDSATOUTOUT25.11005.2502=⋅==∆=∆−−−−µCopyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 18: 10/3/01 A.R. NeureutherVersion Date 10/30/01Switched Equivalent Resistance ModelThe above model assumes the device is an ideal constant current source.1) This is not true below VOUT-SAT-D and leads to in accuracies.2) Combining ideal current sources in networks with series and parallel connections is problematic.OUTDDSATOUTDDOUTCRIVCt 69.02==∆−−Instead define an equivalent resistance for the device by setting 0.69RDC equal to the ∆t found above()Ω==≈⋅=−−−−kAVIVIVRDSATOUTDDDSATOUTDDD5.371005434369.02 µThis givesEach device can now be replaced by this equivalent resistor.RDCopyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 18: 10/3/01 A.R. NeureutherVersion Date 10/30/01Switched Equivalent Resistance NetworkABCABCVDDVOUTABCABCVDDVOUTRURURURDRDRDSwitches close when input is high.Switches open when input is high.For convenience in EE 42 we assume RD= RU= 10 kΩCopyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 18: 10/3/01 A.R. NeureutherVersion Date 10/30/01Inverter Propagation Delay∆t = 0.69RDCOUT= 0.69(10kΩ)(50fF) = 345 psDischarge (pull-down)Discharge (pull-up)∆t = 0.69RUCOUT= 0.69(10kΩ)(50fF) = 345 psVOUTVDDVIN =VddCOUT= 50fFVOUTVDDVIN = VddRDCOUT= 50fFCopyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 18: 10/3/01 A.R. NeureutherVersion Date 10/30/01Logic Gate Propagation Delay: Initial StateThe initial state depends on the old (previous) inputs.The equivalent resistance of the pull-down or pull-up network for the transient phase depends on the new (present) input state.ABCABCVDDVOUTRURURURDRDRDCOUT= 50 fFExample: A=0, B=0, C=0 for a long time.These inputs provided a path to VDD for a long time and the capacitor has precharged up to VDD= 5V.Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 18: 10/3/01 A.R. NeureutherVersion Date 10/30/01Logic Gate Propagation Delay: TransientAt t=0, B and C switch from low to high (VDD) and A remains low. ABCABCVDDVOUTRURURURDRDRDCOUT= 50 fFCOUTdischarges through the pull-down resistance of gates B and C in series.∆t = 0.69(RDB+RDC)COUT= 0.69(20kΩ)(50fF) = 690 psThe propagation delay is two times longer than that for the inverter!This breaks the path from VOUTto VDDAnd opens a path from VOUTto GNDCopyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 18: 10/3/01 A.R. NeureutherVersion Date 10/30/01Logic Gate: Worst Case ScenariosABCABCVDDVOUTRURURURDRDRDWhat combination of previous and present logic inputs will make the Pull-Down the fastest?What combination of previous and present logic inputs will make the Pull-Down the slowest?What combination of previous and present logic inputs will make the Pull-Up the fastest?What combination of previous and present logic inputs will make the Pull-Up the slowest?Fastest overall?Slowest overall?Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 18: 10/3/01 A.R. NeureutherVersion Date 10/30/01Logic Gate CascadeA2B2VDDA1B1A1B1VDDVOUT 1B2C2A2C2VOUT 2To avoid large resistance due to many gates in series, logic functions with 4 or more inputs are usually made from cascading two or more 2-4 input blocks.B2 = VOUT 1The four independent input are A1, B1, A2 and C2.A2 high discharges gate 2 without even waiting for the output of gate 1.C2 high and A2 low makes gate 2 wait for Gate 1 outputCopyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 18: 10/3/01 A.R. NeureutherVersion Date 10/30/01Switched Equivalent Resistance ValuesThe resistor values depend on the properties of silicon, geometrical layout, design style and technology node.n-type silicon has a carrier mobility that is 2 to 3 times higher than p-type.The resistance is inversely proportion to the gate width/length in the geometrical layout.Design styles may restrict all NMOS and PMOS to be of a predetermined fixed size.The current per unit width of the gate increases nearly inversely with the linewidth.Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 18: 10/3/01 A.R. NeureutherVersion Date 10/30/01CMOS Device Parameters at 0.25µm3010.4PMOS1150.630.43NMOSk’ (µA/V2)VOUT-SAT (V)VT(V)Gate length is 0.25 µm = 250 nmA minimum sized device has W =0.5 µm and L = 0.25 µm so W/L=2VDD= 2.5V()AVVVVAIDSATOUTµµ
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