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Berkeley ELENG 42 - Lecture Notes

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Week 9a, Slide 1EECS42, Spring 2005 Prof. WhiteWeek 9aOUTLINE• MOSFET IDvs. VGScharacteristic • Circuit models for the MOSFET– resistive switch model– small-signal modelReading• Rabaey et al.: Chapter 3.3.2• Hambley: Chapter 12 (through 12.5); Section 10.8 (Linear Small-Signal Equivalent Circuits)Week 9a, Slide 2EECS42, Spring 2005 Prof. WhiteIDvs. VDSCharacteristicsThe MOSFET ID-VDScurve consists of two regions:1) Resistive or “Triode” Region: 0 < VDS< VGS− VT2) Saturation Region: VDS> VGS− VT()oxnnTGSnDSATCkVVLWkIµ=′−′= where22oxnnDSDSTGSnDCkVVVVLWkIµ=′⎥⎦⎤⎢⎣⎡−−′= where2process transconductance parameter“CUTOFF” region: VG< VTWeek 9a, Slide 3EECS42, Spring 2005 Prof. WhiteOverview of NMOSFET Regions1. Cutoff region:Conditions: VGS< VT, any value of VDSID= 02. Linear (or Resistive, or Triode) region:VGS> VT, (VGS–VT) > VDSID= (f1x f2x f3)VDSwheref1= µCox(depends on the fabrication process)f2= W/L (chosen by the design engineer)f3= f3(VGS, VT, VDS) = [VGS–VT–VDS/2]~ (VGS–VT) if (VGS–VT) >> VDS/23. Saturation region:VDS> (VGS–VT) = VDSaturation = (VGS–VT)2ID= (1/2) f1x f2x (VGS–VT)2Week 9a, Slide 4EECS42, Spring 2005 Prof. WhiteMOSFET IDvs. VGSCharacteristicLong-channel MOSFETVDS= 2.5 V > VDSATShort-channel MOSFETVDS= 2.5 V > VDSAT• Typically, VDSis fixed when IDis plotted as a function of VGSWeek 9a, Slide 5EECS42, Spring 2005 Prof. WhiteMOSFET VTMeasurement• VTcan be determined by plotting IDvs. VGS, using a low value of VDS :DSDSTGSnDVVVVLWkI⎥⎦⎤⎢⎣⎡−−′=2ID(A)VGS(V)VT0Week 9a, Slide 6EECS42, Spring 2005 Prof. WhiteSubthreshold Conduction (Leakage Current)• The transition from the ON state to the OFF state is gradual. This can be seen more clearly when IDis plotted on a logarithmic scale:• In the subthreshold(VGS< VT) region,This is essentially the channel-source pn junction current.(n, the emission factor, is between 1 and 2)(Some electrons diffuse from thesource into the channel, if thispn junction is forward biased.)⎟⎠⎞⎜⎝⎛∝nkTqVIGSDexpVDS> 0Week 9a, Slide 7EECS42, Spring 2005 Prof. WhiteQualitative Explanation for Subthreshold Leakage• The channel Vc(at the Si surface) is capacitivelycoupled to the gate voltage VG:oxdepoxdepoxCCCCCn +=+=⇒ 1 CoxCdep+Vc–VGUsing the capacitive voltage divider formula:p-type Sin+ poly-Sin+ n+depletion regionVGCIRCUIT MODELDEVICEThe forward bias on the channel-source pnjunction increases withVGscaled by the factor Cox/ (Cox+Cdep)VDGdepoxoxcVCCCV ∆+=∆AdepSidepNWC1∝=εWdepWeek 9a, Slide 8EECS42, Spring 2005 Prof. WhiteSlope Factor (or Subthreshold Swing) S• S is defined to be the inverse slope of the log (ID) vs. VGScharacteristic in the subthreshold region:VDS> 01/S is the slope)10ln(⎟⎟⎠⎞⎜⎜⎝⎛≡qkTnSUnits: Volts per decadeNote that S ≥ 60 mV/decat room temperature:mV 60)10ln( =⎟⎟⎠⎞⎜⎜⎝⎛qkTWeek 9a, Slide 9EECS42, Spring 2005 Prof. WhiteVTDesign Trade-Off(Important consideration for digital-circuit applications)• Low VTis desirable for high ON currentIDSAT∝ (VDD - VT)η1 < η< 2where VDDis the power-supply voltage…but high VTis needed for low OFF currentLow VTHigh VTIOFF,high VTIOFF,low VTVGSlog IDS0Week 9a, Slide 10EECS42, Spring 2005 Prof. WhiteThe MOSFET as a Resistive Switch• For digital circuit applications, the MOSFET is either OFF (VGS< VT) or ON (VGS= VDD). Thus, we only need to consider two IDvs. VDScurves:1. the curve for VGS< VT2. the curve for VGS= VDDIDVDSVGS= VDD (closed switch)VGS< VT(open switch)ReqWeek 9a, Slide 11EECS42, Spring 2005 Prof. WhiteEquivalent Resistance Req• In a digital circuit, an n-channel MOSFET in the ON state is typically used to discharge a capacitor connected to its drain terminal:– gate voltage VG= VDD– source voltage VS= 0 V– drain voltage VDinitially at VDD, discharging toward 0 VThe value of Reqshould be set to the value which gives the correct propagation delay (time required for output to fall to ½VDD):Cload⎟⎠⎞⎜⎝⎛−≅DDnDSATnDDeqVIVRλ65143()22TnDDnDSATnVVLWkI −′=Week 9a, Slide 12EECS42, Spring 2005 Prof. WhiteFigure 0.1 CMOS circuits and their schematic symbols==+Vdd+VddWeek 9a, Slide 13EECS42, Spring 2005 Prof. WhiteTypical MOSFET Parameter Values• For a given MOSFET fabrication process technology, the following parameters are known:– VT (~0.5 V)– Coxand k′(<0.001 A/V2)– VDSAT (≤ 1 V)– λ (≤ 0.1 V-1)Example Reqvalues for 0.25 µm technology (W = L):How can Reqbe decreased?Week 9a, Slide 14EECS42, Spring 2005 Prof. WhiteP-Channel MOSFET Example• In a digital circuit, a p-channel MOSFET in the ON state is typically used to charge a capacitor connected to its drain terminal:– gate voltage VG= 0 V– source voltage VS= VDD(power-supply voltage)– drain voltage VDinitially at 0 V, charging toward VDDCload⎟⎠⎞⎜⎝⎛−≅DDpDSATpDDeqVIVRλ65143VDD0 ViD()22TpDDpDSATVVLWkI −′−=Week 9a, Slide 15EECS42, Spring 2005 Prof. WhiteCommon-Source (CS) Amplifier• The input voltage vscauses vGSto vary with time, which in turn causes iDto vary.VDDRD+vOUT= vDS−+vIN= vGS−+–VBIASvs−+iD• The changing voltage drop across RDcauses an amplified (and inverted) version of the input signal to appear at the drain terminal.Week 9a, Slide 16EECS42, Spring 2005 Prof. WhiteNotation• Subscript convention: VDS≡ VD– VS , VGS≡ VG– VS , etc.• Double-subscripts denote DC sources: VDD , VCC , ISS, etc.• To distinguish between DC and incremental components of an electrical quantity, the following convention is used:– DC quantity: upper-case letter with upper-case subscript ID, VDS , etc.– Incremental quantity: lower-case letter with lower-case subscript id, vds, etc.– Total (DC + incremental) quantity: lower-case letter with upper-case subscript iD, vDS, etc.Week 9a, Slide 17EECS42, Spring 2005 Prof. WhiteLoad-Line Analysis of CS Amplifier• The operating point of the circuit can be determined by finding the intersection of the appropriate MOSFET iDvs. vDScharacteristic and the load line:DSDDDDviRV+=vGS(V)vDS(V)iD(mA)load-line equation:Week 9a, Slide 18EECS42, Spring 2005 Prof. WhiteVoltage Transfer Function(1): transistor biased in cutoff region(2): vIN> VT; transistor biased in saturation region(3): transistor biased in saturation region(4): transistor biased in “resistive” or “triode” regionGoal: Operate the amplifier in the high-gain region, so that small


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Berkeley ELENG 42 - Lecture Notes

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