1Copyright 2003, Regents of University of CaliforniaLecture 20: 11/4//03 A.R. NeureutherVersion Date 11/01/03EECS 42 Intro. Digital Electronics Fall 2003EECS 42 Introduction to Electronics for Computer ScienceAndrew R. NeureutherLecture # 20 Logic TransientsHandout of Monday Lecture. A) 2ndMidterm Review (Cont.)B) Intenal Path Propagation DelayC) Cascade CMOS elementsD)Logic Feedback creates memoryhttp://inst.EECS.Berkeley.EDU/~ee42/Copyright 2003, Regents of University of CaliforniaLecture 20: 11/4//03 A.R. NeureutherVersion Date 11/01/03EECS 42 Intro. Digital Electronics Fall 2003OP-AMP AND USE OF FEEDBACKA very high-gain differential amplifier can function in an extremely linear fashion as an operational amplifier by using negative feedback.Negative feedback ⇒ Stabilizes the outputR2R1−+V0VINEXAMPLEWe can show that that for A →∞and Ri→ ∞,121IN0RRRVV+⋅≅+−+−V0AV1-+V1RiR2Circuit ModelR1VINStable, finite, and independent of the properties of the OP AMP !Copyright 2003, Regents of University of CaliforniaLecture 20: 11/4//03 A.R. NeureutherVersion Date 11/01/03EECS 42 Intro. Digital Electronics Fall 2003IDEAL OP-AMPS ANALYSIS TECHNIQUEAssumption 1: The potential between the op-amp input terminals, v(+)–v(-), equals zero.R2R1−+V0VINEXAMPLEAssumption 2: The currents flowing into the op-amp’s two input terminals both equal zero.No Potential DifferenceNo CurrentsCopyright 2003, Regents of University of CaliforniaLecture 20: 11/4//03 A.R. NeureutherVersion Date 11/01/03EECS 42 Intro. Digital Electronics Fall 2003CASCADE OP-AMP CIRCUITSV1+−V3V2RFR1R2R3V0+−1K9KIINHow do you get started on finding VO?Hint: IINdoes not affect VO1See the further examples of op-amp circuits in the readerHint: Identify StagesCopyright 2003, Regents of University of CaliforniaLecture 20: 11/4//03 A.R. NeureutherVersion Date 11/01/03EECS 42 Intro. Digital Electronics Fall 2003Composite Current Plot for the 42S_NMOSCircuit with 200kΩ Load to GroundVIN= 0 & 1VOUT(V)035IOUT(µA)2060100VIN = 3VIN= 5VTHEVENIN (Open Load)INORTON (Open Load)VTHEVENIN (200KΩ Load) = 3. 3 VINORTON (200KΩ Load)VOUTIOUTOutputVINVDDRPULL UPRLOAD(200KΩ)Copyright 2003, Regents of University of CaliforniaLecture 20: 11/4//03 A.R. NeureutherVersion Date 11/01/03EECS 42 Intro. Digital Electronics Fall 2003VIN= 5Composite IOUTvs. VOUT to Find Points That Satisfies Both Devices for Each VINIOUT(µA)2060100VIN = 3VIN=0 Solution PointsVOUT(V)035VIN=0 & 1IOUT(µA)2060100VIN = 3VIN= 52Copyright 2003, Regents of University of CaliforniaLecture 20: 11/4//03 A.R. NeureutherVersion Date 11/01/03EECS 42 Intro. Digital Electronics Fall 2003Voltage Transfer Function for the Complementary Logic CircuitVOUT(V)VIN(V)035350State 1 for VIN= 1VState 3 for VIN= 3VState 5 for VIN = 5VVMVOUT= VINVertical section due to zero slope of IOUTvs. VOUTin the saturation region of both devices.VTUVTDVOUT-SAT-DVOUT-SAT-UPD-OffPU-OffCopyright 2003, Regents of University of CaliforniaLecture 20: 11/4//03 A.R. NeureutherVersion Date 11/01/03EECS 42 Intro. Digital Electronics Fall 2003Switched Equivalent Resistance NetworkABCABCVDDVOUTABCABCVDDVOUTRURURURDRDRDSwitches close when input is high.Switches close when input is low.Copyright 2003, Regents of University of CaliforniaLecture 20: 11/4//03 A.R. NeureutherVersion Date 11/01/03EECS 42 Intro. Digital Electronics Fall 2003Logic Gate Propagation Delay: Initial StateThe initial state depends on the old (previous) inputs.The equivalent resistance of the pull-down or pull-up network for the transient phase depends on the new (present) input state.ABCABCVDDVOUTRURURURDRDRDCOUT= 50 fFExample: A=0, B=0, C=0 for a long time.These inputs provided a path to VDD for a long time and the capacitor has precharged up to VDD= 5V.Copyright 2003, Regents of University of CaliforniaLecture 20: 11/4//03 A.R. NeureutherVersion Date 11/01/03EECS 42 Intro. Digital Electronics Fall 2003Logic Gate Propagation Delay: TransientAt t=0, B and C switch from low to high (VDD) and A remains low. ABCABCVDDVOUTRURURURDRDRDCOUT= 50 fFCOUTdischarges through the pull-down resistance of gates B and C in series.∆t = 0.69(RDB+RDC)COUT= 0.69(20kΩ)(50fF) = 690 psThe propagation delay is two times longer than that for the inverter!This breaks the path from VOUTto VDDAnd opens a path from VOUTto GNDCopyright 2003, Regents of University of CaliforniaLecture 20: 11/4//03 A.R. NeureutherVersion Date 11/01/03EECS 42 Intro. Digital Electronics Fall 2003Logic Gate: Worst Case ScenariosWhat combination of previous and present logic inputs will make the Pull-Down the fastest?What combination of previous and present logic inputs will make the Pull-Down the slowest?What combination of previous and present logic inputs will make the Pull-Up the fastest?What combination of previous and present logic inputs will make the Pull-Up the slowest?Fastest overall?Slowest overall?ABCABCVDDVOUTRURURURDRDRDCOUT= 50 fFCopyright 2003, Regents of University of CaliforniaLecture 20: 11/4//03 A.R. NeureutherVersion Date 11/01/03EECS 42 Intro. Digital Electronics Fall 2003Logic Gate CascadeTo avoid large resistance due to many gates in series, logic functions with 4 or more inputs are usually made from cascading two or more 2-4 input blocks.B2 = VOUT 1The four independent input are A1, B1, A2 and C2.A2 high discharges gate 2 without even waiting for the output of gate 1.C2 high and A2 low makes gate 2 wait for Gate 1 outputA2B2VDDA1B1A1B1VDDVOUT 1B2C2A2C2VOUT 250 fF50 fF3Copyright 2003, Regents of University of CaliforniaLecture 20: 11/4//03 A.R. NeureutherVersion Date 11/01/03EECS 42 Intro. Digital Electronics Fall 2003Feedback Can Provide MemoryQQHHLLHHCopyright 2003, Regents of University of CaliforniaLecture 20: 11/4//03 A.R. NeureutherVersion Date 11/01/03EECS 42 Intro. Digital Electronics Fall 2003Example of the Opposite StateQQHHLHHLCopyright 2003, Regents of University of CaliforniaLecture 20: 11/4//03 A.R. NeureutherVersion Date 11/01/03EECS 42 Intro. Digital Electronics Fall 2003Adding Memory ControlsQQSRSet-Reset Flip-FlopCopyright 2003, Regents of University of CaliforniaLecture 20: 11/4//03 A.R. NeureutherVersion Date 11/01/03EECS 42 Intro. Digital Electronics Fall 2003Adding a ClockSRQQCKClocked S-R
View Full Document