1Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Spring 2003 Lecture 26: 5/7/03 A.R. NeureutherVersion Date 4/30/03Calbot Contest Monday 5/12Jason Gatt and Kevin Ha“Best in Show” inTutbot/CalbotContest F00Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Spring 2003 Lecture 26: 5/7/03 A.R. NeureutherVersion Date 4/30/03Review of Basic Circuit ConceptsSheila RossLecture ReviewCircuit AnalysisTransientsLogicTiming DiagramsDependent Sources and Op-AmpsLoad Line and VOUTvs VINDiodesMOS Operation2Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Spring 2003 Lecture 26: 5/7/03 A.R. NeureutherVersion Date 4/30/03RVoutVCo0=+−5VRC1µsec=CPULSE: Output is Rising exponential then Falling exponentialExample: Switch rises at t =0, falls at t = 0.1, 1 or 10µsec (Do 1µsec case)Solution: for RC = 1µsec: during the first rise V obeys:0123456012345time (microseconds)Vout610te1[5V−−−=]Now starting at 1µsec we aredischarging the capacitor so the form is a falling exponential withinitial value 3.16 V:Thus at t = 1µsec, rising voltage reaches]e1[5=−-13.16VWhat is equation?Lecture 7Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Spring 2003 Lecture 26: 5/7/03 A.R. NeureutherVersion Date 4/30/03EXAMPLE WITH BOTH SPECIAL CASES+_I1R4R1R2R3V2abcd()0423211=+−+−−RVVRRVRVIaaaLecture 83Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Spring 2003 Lecture 26: 5/7/03 A.R. NeureutherVersion Date 4/30/03How to Combine Gate to Produce a Desired Logic Function?(More basic Logical Synthesis)Example:01111011010100011010C010010100000FBAF= C +ABB ACABCABCFCopyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Spring 2003 Lecture 26: 5/7/03 A.R. NeureutherVersion Date 4/30/03Logical SynthesisGuided by DeMorgan’s TheoremDeMorgan’s Theorem :[] C B A CBA =++or[] C BA CBA =++Example of Using DeMorgan’s Theorem:Thus any sum of products expression can be immediately synthesized from NAND gates aloneCDEAB EDC BA F •=••+•=ABCDFE4Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Spring 2003 Lecture 26: 5/7/03 A.R. NeureutherVersion Date 4/30/03Logical Synthesis of XOR011101110000FBABABAF•+•=FBAABBAX•=BAY•=Delay 1Delay 2Delay 3We Need a Timing Diagram!Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Spring 2003 Lecture 26: 5/7/03 A.R. NeureutherVersion Date 4/30/03Timing Diagram for Delays in LogictimeLogic levelABABXYFF = 1F = 05Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Spring 2003 Lecture 26: 5/7/03 A.R. NeureutherVersion Date 4/30/03C,B,AD)BA(+)(__CB⋅BDtttttLogic stateτττ2τ2τ03ττTIMING DIAGRAMSShow transitions of variables vs timeABCNote that becomes valid two gate delays after B&C switch, because the invert function takes one delay and the NAND function a second.)(__CB⋅No change at t = 3τNote becomes valid one gate delay after B switchesB10Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Spring 2003 Lecture 26: 5/7/03 A.R. NeureutherVersion Date 4/30/03GmVcdVoltage-controlled current source … I = GmVcdAiIcCurrent-controlled current source … I = AiIc+-RmIcCurrent-controlled voltage source … V = Rm IcThe 4 Basic Linear Dependent SourcesVoltage-controlled voltage source … V = AvVcdAvVcd+-Parameter being sensedConstant of proportionalityOutputLecture 136Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Spring 2003 Lecture 26: 5/7/03 A.R. NeureutherVersion Date 4/30/03EXAMPLE CIRCUIT: INCREASED OUTPUT RESISTANCERINv = 0 vIN + - +-GmvIN +-vTEST ROiTEST REvE Add resistor REAnalysis: apply iTESTand evaluate vTESTUnknowns: iTEST, vTEST, vIN, vENeed 3 equations to find the ratio of iTEST/ vTESTvIN= -vE and is not zero!KCL at vEKVL at vOUTIntuitive Explanation: GmVINburps currentwhich has to also go through R0. This raises vTESTand the output impedance vTEST/iTESTThe input has been assumed to be shortedTry a bag. It is even easierFinish this in the homeworkCopyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Spring 2003 Lecture 26: 5/7/03 A.R. NeureutherVersion Date 4/30/03CASCADE OP-AMP CIRCUITSV1+−V3V2RFR1R2R3V0+−1K9KIINHow do you get started on finding VO?Hint: IINdoes not affect VO1See the further examples of op-amp circuits in the readerHint: Identify Stages7Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Spring 2003 Lecture 26: 5/7/03 A.R. NeureutherVersion Date 4/30/03Composite Current Plot for the 42PDCircuit with 200kΩ Load to GroundState 1VOUT(V)035IOUT(µA)2060100State 3State 5VTHEVENIN (Open Load)INORTON (Open Load)VTHEVENIN (200KΩ Load) = 3. 3 VINORTON (200KΩ Load)VOUTIOUTOutputVINVDDRPULL UPRLOAD(200KΩ)Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Spring 2003 Lecture 26: 5/7/03 A.R. NeureutherVersion Date 4/30/03Voltage Transfer Function for the 42PD Logic Circuit w/wo LoadVOUT(V)VIN(V)035350State 1State 3State 5Open Load200 KΩ LoadComplete this VTC for the 42PD device in the HomeworkLecture 158Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Spring 2003 Lecture 26: 5/7/03 A.R. NeureutherVersion Date 4/30/03Feedback Can Provide MemoryQQHHLLHHLecture 19Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Spring 2003 Lecture 26: 5/7/03 A.R. NeureutherVersion Date 4/30/03DIODE I-V CHARACTERISTICS AND MODELSThe equationis graphed below for 1)kTqVexp(II0−=A10I150−=The characteristic is described as a “rectifier” – that is, a device that permits current to pass in only one direction. (The hydraulic analog is a “check value”.) Hence the symbol:+− VISimple “Perfect Rectifier” ModelIf we can ignore the small forward-bias voltage drop of a diode, a simple effective model is the “perfect rectifier,” whose I-V characteristic is given below:VIReverse bias0Vany ,0I<≅Forward bias0Iany ,0V >≅A perfect rectifier0246810-5 0 5 10Current in mAForward Voltage in V9Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Spring 2003 Lecture 26: 5/7/03 A.R. NeureutherVersion Date
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