PowerPoint PresentationEdge triggeringEdge-Triggered Flip-FlopsEdge-Triggered Flip-Flops (cont’d)Timing MethodologiesSlide 6Definition: Set up time/hold timeComparison of Latches and Flip-FlopsComparison of Latches and Flip-Flops (cont’d)Typical Timing SpecificationsCascading Edge-triggered Flip-FlopsCascading Edge-triggered Flip-Flops (cont’d)Clock SkewSummary of Latches and Flip-FlopsFlip-Flop FeaturesRegistersShift RegisterShift Register ApplicationPattern RecognizerBinary CounterSequential Logic Summary11/15/2004 EE 42 fall 2004 lecture 32 1Lecture #32 Registers, counters etc.•Last lecture: –Digital circuits with feedback–Clocks–Flip-Flops•This Lecture:–Edge triggers–Registers–shift registers–counters11/15/2004 EE 42 fall 2004 lecture 32 2Edge triggering•The last lecture ended with how a flip flop could be designed by using two latches which cascaded in a master-slave relationship.•Another way of creating an edge triggered flip flop is to use logic with feedback, as in the following slide.11/15/2004 EE 42 fall 2004 lecture 32 3QDClk=1RSQ’negative edge-triggered D flip-flop (D-FF)4-5 gate delaysmust respect setup and hold time constraints to successfullycapture inputcharacteristic equationQ(t+1) = Dholds D' whenclock goes lowholds D whenclock goes lowEdge-Triggered Flip-Flops•More efficient solution: only 6 gates–sensitive to inputs only near edge of clock signal (not while high)11/15/2004 EE 42 fall 2004 lecture 32 4positive edge-triggered FFnegative edge-triggered FFDCLKQposQpos'QnegQneg'100Edge-Triggered Flip-Flops (cont’d)•Positive edge-triggered–Inputs sampled on rising edge; outputs change after rising edge•Negative edge-triggered flip-flops–Inputs sampled on falling edge; outputs change after falling edge11/15/2004 EE 42 fall 2004 lecture 32 5Timing Methodologies•As we have seen, there are several different ways of designing a sequential logic circuit. In general, each circuit will stick with a set of rules which are designed to achieve consistently accurate results.•A set of rules for interconnecting components and clocks are adopted which will guarantee proper operation of system when strictly followed.•Approach depends on building blocks used for memory elements. Edge-triggered flip-flops are found in programmable logic devices•Many custom integrated circuits focus on level-sensitive latches11/15/2004 EE 42 fall 2004 lecture 32 6•Basic rules for correct timing:–Inputs to flip-flops are stable and correct for and interval around the time of sampling (avoid asynchronous inputs wherever possible)–No flip-flop changes state more than once per clocking event11/15/2004 EE 42 fall 2004 lecture 32 7clockdatachangingstableinputclockTsuThclockdataD Q D QDefinition: Set up time/hold timeTo ensure that the data signal is captured accurately, the data must be stable for an time tsu (set up) before the edge, and kept constant for a time th (hold) after the edge.11/15/2004 EE 42 fall 2004 lecture 32 8behavior is the same unless input changeswhile the clock is highD QCLKpositiveedge-triggeredflip-flopD QGCLKtransparent(level-sensitive)latchDCLKQedgeQlatchComparison of Latches and Flip-Flops11/15/2004 EE 42 fall 2004 lecture 32 9Type When inputs are sampled When output is validunclocked always propagation delay from input changelatchlevel-sensitive clock high propagation delay from input changelatch (Tsu/Th around falling or clock edge (whichever is later)edge of clock)master-slave clock high propagation delay from falling edgeflip-flop (Tsu/Th around falling of clockedge of clock)negative clock hi-to-lo transition propagation delay from falling edgeedge-triggered (Tsu/Th around falling of clockflip-flop edge of clock)Comparison of Latches and Flip-Flops (cont’d)11/15/2004 EE 42 fall 2004 lecture 32 10all measurements are made from the clocking event that is, the rising edge of the clockTypical Timing Specifications•Positive edge-triggered D flip-flop–Setup and hold times–Minimum clock width–Propagation delaysTh0.5 nsTw 1nsTsu0.8 nsDCLKTsu0.8 nsTh0.5 ns11/15/2004 EE 42 fall 2004 lecture 32 11INQ0Q1CLK100Cascading Edge-triggered Flip-Flops•Shift register–New value goes into first stage–While previous value of first stage goes into second stage–The propagation time must be longer than the hold timeCLKINQ0 Q1D Q D QOUT11/15/2004 EE 42 fall 2004 lecture 32 12timing constraintsguarantee properoperation ofcascaded componentsassumes infinitely fast distribution of the clockCascading Edge-triggered Flip-Flops (cont’d)•Why this works–Propagation delays exceed hold times–Clock width constraint exceeds setup time–This guarantees following stage will latch current value before it changes to new valueTsu4nsTp3nsTh2nsInQ0Q1CLKTsu4nsTp3nsTh2ns11/15/2004 EE 42 fall 2004 lecture 32 13original state: IN = 0, Q0 = 1, Q1 = 1due to skew, next state becomes: Q0 = 0, Q1 = 0, and not Q0 = 0, Q1 = 1CLK1 is a delayedversion of CLK0InQ0Q1CLK0CLK1100Clock Skew•The problem–Correct behavior assumes next state of all storage elementsdetermined by all storage elements at the same time–This is difficult in high-performance systems because time for clock to arrive at flip-flop is comparable to delays through logic–Effect of skew on cascaded flip-flops:11/15/2004 EE 42 fall 2004 lecture 32 14 Summary of Latches and Flip-Flops•Development of D-Flip-Flop–Level-sensitive used in custom integrated circuits•can be made with 4 gates–Edge-triggered used in programmable logic devices–Good choice for data storage register•Historically J-K Flip Flop was popular but now never used–Similar to R-S but with 1-1 being used to toggle output (complement state)–Can always be implemented using D-FF•Preset and clear inputs are highly desirable on flip-flops–Used at start-up or to reset system to a known state11/15/2004 EE 42 fall 2004 lecture 32 15Flip-Flop Features•Reset (set state to 0) – R–Synchronous: Dnew = R' • Dold (when next clock edge arrives)–Asynchronous: doesn't wait for clock, quick but dangerous•Preset or set (set state to 1) – S (or sometimes P)–Synchronous: Dnew = Dold + S (when next clock edge arrives)–Asynchronous: doesn't wait for clock, quick but dangerous•Both reset and preset–Dnew = R' • Dold + S (set-dominant)–Dnew = R' • Dold + R'S (reset-dominant)•Selective input capability (input enable/load) – LD or EN–Multiplexer at input: Dnew = LD' • Q + LD •
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