04/19/03 Problem Set # 10 Due 4:30 PM April 30th, 240 Cory Reading: Week 13# Diodes and MOS Devices, S&O 13.1-13.2, 518-526. This is an easy but instructive problem set to walk you through data dependent propagation delays and the maximum clock frequency. Use the circuits for Gate1 and Gate2 below. Throughout this problem make the simplifying assumption that each gate or latch stage has a load of 50 fF and that each ‘on’ transistor has a resistance of 10kΩ. That is RD = RU = 10 kΩ. The inverter delay is 0.69(10kΩ)50fF = 345 ps. 10.1 Data Dependence of Single-Gate Delay. a) Determine the logic function of Gate1 and Gate2. b) Describe 3 features that combine together to make these gates complementary. c) Find the minimum and maximum propagation delay τHL for the output going from high to low for each of the gates. Give the data dependent range of delays compared to a simple inverter (such as ½ to 7/3 the inverter delay). d) Find the minimum and maximum propagation delay τLH for the output going from low to high for each of the gates. Give the data dependent range of delays. e) Give the worst case over-all range of data dependent delays. 10.2 Data Dependence of Cascade-Gate Delay. For this problem assume that the output of Gate1 is connected to the input A2 of Gate2 and that the capacitive loads remain unchanged. a) Determine the shortest propagation delay for the output of Gate2 to change compared to an inverter and give a set of initial inputs and input changes that produce it. b) Determine the longest propagation delay for the output of Gate2 to change compared to an inverter and give a set of initial inputs and input changes that produce it. 10.3 Lumped vs. Pipelined Logic. Latches are now introduced to synchronize transfer of logic outputs among circuits as shown below. There are two implementations. In the lumped implementation the cascade of Gate1/Gate2 from 10.2 is placed after a latch L0 that releases B1 and the cascade circuit is followed by and output hold latch L1. In the pipelined implementation the latch L0 that releases B1 is followed first by Gate1 alone, then an output hold latch L1, then Gate2 and finally an output hold latch L2. Assume that the inputs have been A1 = 1, B1 = 1, C1 = 0, D1 = 1, E1 = 0, A = VOUT1, B2=1, C2 = 1, D2 =1 for a long time. However, prior to the rising edge of the clock at t = 0, the first stage in L0 has permanently gone high so that on the rising edge B1 starts its transition to 0. a) Determine the propagation delay of the latch circuit for both the rising edge and falling edge of the clock in units of inverter delay. b) Sketch the output of Gate1(VOUT1) and the output of Latch1 (VLATCH1) versus time in the a timing diagram for the lumped implementation. (Assume clock goes up for 10 inverter delays and then down for 10 inverter delays). c) Sketch the output of Gate1(VOUT1), the output of Latch1 (VLATCH1), the output of Gate2(VOUT2), the output of Latch2 (VLATCH2) versus time in the timing diagram for the pipeline implementation using the clock from b). 10.4 Latency and Throughput of Lumped and Piplined Logic. a) Determine the maximum data dependent latch-to-latch delay of the lumped implementation. This is the time from the rising clock edge on the input release latch L0 until the next possible rising clock edge. That is the output of L0 must change, the Gate1 EECS 42 – Introduction to Electronics for Computer Science Spring 2003, Prof. A. R. Neureuther Dept. EECS, 510 Cory [email protected] 642-4590 UC Berkeley Office Hours (Tentative M, Tu, W, (Th), F 11 Course Web Site http://www-inst.eecs.berkeley.edu/~ee42/04/19/03 must react, Gate2 must the react and finally the clock must go low long enough for latch L1 input stage to react. (Hint: Add the delays in clock high and those in clock low.) b) Determine the maximum data dependent latch-to-latch delay of each sub-section of the pipeline implementation. c) The latency of the overall logic evaluation is the time for the data to appear on the final output latch. Find the latency for the lumped and pipeline implementations in terms of a number of inverter delays. (Be sure to us the output of L2 for the pipeline). d) The minimum clock period must be larger than the maximum latch-to-latch delay. The maximum clock frequency is the inverse of the minimum clock period. Find the minimum clock period for the lumped and pipelined implementations. The clock need not go low for as long as it goes high. Assuming one computed result comes out per clock cycle, how much faster is the pipeline architecture than the lumped architecture? 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