1Copyright 2003, Regents of University of CaliforniaLecture 25: 12/02/03 A.R. NeureutherVersion Date 11/30/03EECS 42 Intro. Digital Electronics, Fall 2003EECS 42 Introduction to Digital ElectronicsLecture # 25 MicrofabricationHandout of This Lecture. Today: how are Integrated Circuits made?– Silicon wafers– Oxide formation by growth or deposition– Other films– Pattern transfer by lithographyhttp://inst.EECS.Berkeley.EDU/~ee42/Copyright 2003, Regents of University of CaliforniaLecture 25: 12/02/03 A.R. NeureutherVersion Date 11/30/03EECS 42 Intro. Digital Electronics, Fall 2003Integrated Circuits• J. Kilby, Texas Instruments and R. Noyce, Fairchild, circa 1958.• Make the entire circuit at one time … using concepts borrowed from printing technology• What do we need?– a substrate for the circuit – a way to dope regions of silicon n or p type – insulating and conducting films to form the MOS transistor and interconnect it– processes for etching patterns into these filmsCopyright 2003, Regents of University of CaliforniaLecture 25: 12/02/03 A.R. NeureutherVersion Date 11/30/03EECS 42 Intro. Digital Electronics, Fall 2003Early 21stCentury IC Technology• Many levels of electrical interconnect (Cu)– Ten-level metal is entering production• MOSFET is shrinking: – gate lengths of 10 nm = 0.01 µm have been demonstrated by Intel, TSMC, AMD, Æ new device structures are based on late 1990s UC Berkeley research (Profs. Hu, King, and Bokor)• Technology/economic limits …– Roadblocks to increasing density are a huge challenge around 2015 Copyright 2003, Regents of University of CaliforniaLecture 25: 12/02/03 A.R. NeureutherVersion Date 11/30/03EECS 42 Intro. Digital Electronics, Fall 2003Complexity of IC MetallizationIBM Microelectronics GalleryColorized scanning-electronmicrograph of the copper inter-connect layers, after removalof the insulating layers by achemical etchNote: all > 108connectionsmust work or the chip doesn’tfunction. Current Berkeleyresearch (Prof. Bora Nikolic)is directed at fault-tolerantdesign methodologiesCopyright 2003, Regents of University of CaliforniaLecture 25: 12/02/03 A.R. NeureutherVersion Date 11/30/03EECS 42 Intro. Digital Electronics, Fall 2003Silicon Substrates (Wafers)Crystals are grown from the melt in boules (cylinders) with specified dopant concentrations. They are ground perfectly round and oriented (a “flat” is ground along the boule) and then sliced like salami into wafers. 200 mm = 20 cm“flat indicatescrystal orientationTypical wafer cost: $50Sizes: Today 200 mm or 300 mm in diameterCopyright 2003, Regents of University of CaliforniaLecture 25: 12/02/03 A.R. NeureutherVersion Date 11/30/03EECS 42 Intro. Digital Electronics, Fall 2003Adding Dopants to SiliconA finished wafer can have dopants added to its surface by a combination of ion implantation and annealing (heating the silicon wafer to > 800oCFeatures: crystal structure of the wafer is destroyed due to ion impact at energies of 20 keV – 5 MeV … damage can be as deep as 1 um below surfaceAnnealing heals the damage … nearly perfectly. The B or As or P atoms end up as substitutional impurities on lattice sites2Copyright 2003, Regents of University of CaliforniaLecture 25: 12/02/03 A.R. NeureutherVersion Date 11/30/03EECS 42 Intro. Digital Electronics, Fall 2003Thermal oxidation grows SiO2on Si, but it consumes Si from the substrate, so the wafer gets thinner. Suppose we grow 1µm of oxide:THERMAL OXIDATION OF SILICONSilicon wafer before = 500µm thickSilicon wafer after = 500µm thick plus 1µm of oxide all around for a total thickness of 501µm .500 µm501 µmCopyright 2003, Regents of University of CaliforniaLecture 25: 12/02/03 A.R. NeureutherVersion Date 11/30/03EECS 42 Intro. Digital Electronics, Fall 2003Now suppose we grow 0.1µm of SiO2:THERMAL OXIDATION OF SILICON (continued)Thermal oxidation rate slows with oxide thickness, so thick films hardly increase their thickness during growth of a thin film at a different position on the wafer. Consider starting with the following structure:Oxide thickness = 1 µmBare region of waferCopyright 2003, Regents of University of CaliforniaLecture 25: 12/02/03 A.R. NeureutherVersion Date 11/30/03EECS 42 Intro. Digital Electronics, Fall 2003Deposited IC MaterialsPolycrystalline silicon (polysilicon or simply “poly”)Wafer is heated to around 600 oC and a silicon-containing gas (SiH4) is passed over it; a surface reaction results in a deposited layer of silicon: SiH4 = Si + 2H2Properties: Sheet resistance can be fairly low (e.g. if doped heavily and 500 nm thick, R= 20 Ω/ ). It can withstand high temperature anneals. Æ major advantage for MOS gatesSilicon waferSi Film made up of crystallitesSiO2Terminology: “CVD” =Chemical Vapor DepositionCopyright 2003, Regents of University of CaliforniaLecture 25: 12/02/03 A.R. NeureutherVersion Date 11/30/03EECS 42 Intro. Digital Electronics, Fall 2003More Deposited MaterialsSilicon Dioxide: Similar process (SiH4+ 02) at 425oCuseful as an insulator between conducting layersMetal films: (aluminum and copper)Deposited at near room temperature using a “sputtering” process (Highly energetic argon ions batter the surface of a metal target, knocking atoms of loose which land on the surface of the wafer.)Other films:Special insulating layers with low dielectric constants, thin ceramic films (e.g., TiN) that are useful to keep materials from interacting during subsequent processingCopyright 2003, Regents of University of CaliforniaLecture 25: 12/02/03 A.R. NeureutherVersion Date 11/30/03EECS 42 Intro. Digital Electronics, Fall 2003Patterning the Layers - LithographyFabrication process = sequence of processes in which layers are added or modified and each layer is patterned, that is selectively removed or selectively added according to the circuit desiredPhotolithography: invented circa 1822 by Nicéphore Niépce (France) –early pioneer in photographyProcess for transferring a pattern in parallel (like printing)Equipment , Materials, and Processes needed:1. A mask (… where do we find masks, anyway?)2. A photosensitive material (called photoresist)3. A light source and method of projecting the image of the mask ontothe photoresist (“printer” or “projection stepper” or “projection scanner”)4. A
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