DOC PREVIEW
Berkeley ELENG 42 - Logic Transients

This preview shows page 1-2-3 out of 10 pages.

Save
View full document
View full document
Premium Document
Do you want full access? Go Premium and unlock all 10 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 10 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 10 pages.
Access to all documents
Download any document
Ad free experience
Premium Document
Do you want full access? Go Premium and unlock all 10 pages.
Access to all documents
Download any document
Ad free experience

Unformatted text preview:

1Copyright 2001, Regents of University of CaliforniaLecture 18: 04/0703 A.R. NeureutherVersion Date 04/05/03EECS 42 Intro. electronics for CS Spring 2003EECS 42 Introduction to Electronics for Computer ScienceAndrew R. NeureutherLecture # 18 Logic TransientsHandout of Mon Lecture. A) Quiz 4/9 and Midterm 4/16 review B) Transient as Capacitor Charging C) Equivalent Resistance for MOSD) Inverter Propagation DelayE) Complementary MOS Operationhttp://inst.EECS.Berkeley.EDU/~ee42/Copyright 2001, Regents of University of CaliforniaLecture 18: 04/0703 A.R. NeureutherVersion Date 04/05/03EECS 42 Intro. electronics for CS Spring 2003Game Plan 04/07/03Last Week: Static Logic: NMOS, CMOS; Graphical Solution and VTC) {All of this will be on 2ndMidterm)Monday 4/07/03:R Discharging Capacitors with NMOS and Eq. ResistanceR CMOS Logic and Propagation delayWednesday 04/09/03:R QUIZ: Digital Blocks including timing diagrams and Dependent sources including Op-Amps R Worst Case CMOS delay, Cascade and CMOS LatchNext (11th) Week: Diodes and MOS OperationProblem set #9: Monday 3/31 and due at 2:30 4/09 in box in 240 Cory –Static Analysis of an Inverter with simplified EE 42 Device ModelsNo Problem set for 4/16 as Midterm 4/16: Lectures 1-17 with emphasis on Lectures 10-17; Review Session Monday 5:30-7PM2Copyright 2001, Regents of University of CaliforniaLecture 18: 04/0703 A.R. NeureutherVersion Date 04/05/03EECS 42 Intro. electronics for CS Spring 2003Logical SynthesisGuided by DeMorgan’s TheoremDeMorgan’s Theorem :[] C B A CBA=++or[] C BA CBA =++Example of Using DeMorgan’s Theorem:Thus any sum of products expression can be immediately synthesized from NAND gates aloneCDEAB EDC BA F•=••+•=ABCDFECopyright 2001, Regents of University of CaliforniaLecture 18: 04/0703 A.R. NeureutherVersion Date 04/05/03EECS 42 Intro. electronics for CS Spring 2003EFFECT OF GATE DELAYCascade of Logic GatesABCDInputs have different delays, but we ascribe a single worst-case delay τto every gateHow many “gate delays for shortest path?ANSWER : 2How many gate delays for longest path? ANSWER : 33Copyright 2001, Regents of University of CaliforniaLecture 18: 04/0703 A.R. NeureutherVersion Date 04/05/03EECS 42 Intro. electronics for CS Spring 2003C,B,AD)BA( +)(__CB⋅BDtttttLogic stateτττ2τ2τ03ττTIMING DIAGRAMSShow transitions of variables vs timeABCNote that becomes valid two gate delays after B&C switch, because the invert function takes one delay and the NAND function a second.)(__CB⋅No change at t = 3τNote becomes valid one gate delay after B switchesB10Glitching: temporary switching to an incorrect valueCopyright 2001, Regents of University of CaliforniaLecture 18: 04/0703 A.R. NeureutherVersion Date 04/05/03EECS 42 Intro. electronics for CS Spring 2003EXAMPLE CIRCUIT: INCREASED INPUT RESISTANCERIN vTEST vIN + - + - GmvIN + - vOUT = 0 RO iTEST RE vE Add resistor REAnalysis: apply iTESTand evaluate vTEST00=−−+TESTINmTESTEEEiRGiRvRvTESTININiRv =ETESTINTESTviRv +=KCLEINmINTESTTESTRRGRiv)1(++=Check for special case for R0 infiniteIntuitive Explanation:REputs RINon a node whose voltage increases in response to current in RIN.The output has been assumed to be shortedSimilar to the homework4Copyright 2001, Regents of University of CaliforniaLecture 18: 04/0703 A.R. NeureutherVersion Date 04/05/03EECS 42 Intro. electronics for CS Spring 2003Composite IOUTvs. VOUTfor CMOSVDD=5The maximum voltage is VDDVOUT(V)03IOUT(µA)2060100State 3 or VIN= 3VVOUT-SAT-DPull-Up PMOS IOUT-SAT-UPull-Down NMOS IOUT-SAT-DSolutionPD current is flat (saturated) beyond VOUT-SAT-DPU current is flat (saturated) belowVDD-VOUT-SAT-DCopyright 2001, Regents of University of CaliforniaLecture 18: 04/0703 A.R. NeureutherVersion Date 04/05/03EECS 42 Intro. electronics for CS Spring 2003Method for Finding VMAt VM, 1) VOUT= VIN =VM2) Both devices are in saturation3) IOUT-SAT-D= IOUT-SAT-U()()USATOUTTUINDDUUSATOUTDSATOUTTDINDDSATOUTVVVVkIVVVkI−−−−−−−−−−==−=)SubstituteVMSolve for VMExample Result: When kD= kP, VOUT-SAT-D= VOUT-SAT-Uand VTD=VTU, then VM= VDD/25Copyright 2001, Regents of University of CaliforniaLecture 18: 04/0703 A.R. NeureutherVersion Date 04/05/03EECS 42 Intro. electronics for CS Spring 2003Voltage Transfer Function for the Complementary Logic CircuitVOUT(V)VIN(V)035350State 1 for VIN= 1VState 3 for VIN= 3VState 5 for VIN = 5VVMVOUT= VINVertical section due to zero slope of IOUTvs. VOUTin the saturation region of both devices.VTUVTDVOUT-SAT-DVOUT-SAT-UPD-OffPU-OffCopyright 2001, Regents of University of CaliforniaLecture 18: 04/0703 A.R. NeureutherVersion Date 04/05/03EECS 42 Intro. electronics for CS Spring 2003Transient Gate Problem: Discharging and Charging Capacitance on the OutputVOUTIOUTOutputVIN-DVDDVIN-Up-type MOSTransistor(PMOS)n-type MOSTransistor(NMOS)VIN= VDD= 5VCOUT= 50 fF5V => 06Copyright 2001, Regents of University of CaliforniaLecture 18: 04/0703 A.R. NeureutherVersion Date 04/05/03EECS 42 Intro. electronics for CS Spring 2003Output Propagation Delay High to LowVOUT(0) = 5VCOUT= 50 fFIOUT-SAT-D= 100 µAVOUT(V)035IOUT(µA)2060100VIN= 5VIOUT-SAT-D= 100 µAWhen VINgoes High VOUTstarts decreases with time Assume that the necessary voltage swing to cause the next downstream gate to begin to switch is VDD/2 or 2.5V. That is the propagation delay τHLfor the output to go from high to low is the time to go from VDD= 5V to to VDD/2 =2.5VCopyright 2001, Regents of University of CaliforniaLecture 18: 04/0703 A.R. NeureutherVersion Date 04/05/03EECS 42 Intro. electronics for CS Spring 2003Output Propagation Delay High to Low (Cont.)When VOUT> VOUT-SAT-Dthe available current is IOUT-SAT-DVOUT(0) = 5VCOUT= 50 fFIOUT-SAT-D= 100 µAVOUT(V)035IOUT(µA)2060100VIN= 5VIOUT-SAT-D= 100 µAThe propagation delay is thusnsAVfFIVCIVCtDSATOUTDDOUTDSATOUTOUT25.11005.2502=⋅==∆=∆−−−−µFor this circuit when VOUT> VOUT-SAT-Dthe available current is constant at IOUT-SAT-D and the capacitor discharges.7Copyright 2001, Regents of University of CaliforniaLecture 18: 04/0703 A.R. NeureutherVersion Date 04/05/03EECS 42 Intro. electronics for CS Spring 2003Switched Equivalent Resistance ModelThe above model assumes the device is an ideal constant current source.1) This is not true below VOUT-SAT-D and leads to in accuracies.2) Combining ideal current sources in networks with series and parallel connections is


View Full Document

Berkeley ELENG 42 - Logic Transients

Documents in this Course
Lecture 1

Lecture 1

25 pages

Lecture 2

Lecture 2

20 pages

Lecture 3

Lecture 3

21 pages

Midterm 1

Midterm 1

20 pages

Load more
Download Logic Transients
Our administrator received your request to download this document. We will send you the file to your email shortly.
Loading Unlocking...
Login

Join to view Logic Transients and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view Logic Transients 2 2 and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?