Week 9b, Slide 1EECS42, Spring 2005 Prof. WhiteWeek 9bOUTLINE• Digital logic functions• NMOS logic gates• The CMOS inverterReading• Rabaey et al.: Section 5.2• Hambley: Sections 7.1-7.2 (Logic)Week 9b, Slide 2EECS42, Spring 2005 Prof. WhiteDigital Signals• For a digital signal, the voltage must be within one of two ranges in order to be defined:• Positive Logic:–“low” voltage ≡ logic state 0– “high” voltage ≡ logic state 1“1”“0”VOHVIHVILVOLundefined regionincreasingvoltageVDD0 VoltsWeek 9b, Slide 3EECS42, Spring 2005 Prof. WhiteLogic Functions, Symbols, & Notation“NOT”F = ATRUTHNAMESYMBOL NOTATION TABLEFA111001010000FBA“OR”F = A+BFAB0110FA111101110000FBA“AND”F = A•BFABWeek 9b, Slide 4EECS42, Spring 2005 Prof. White“NOR”F = A+B011101110000FBA“NAND”F = A•BFAB011101110100FBA“XOR”(exclusive OR)F = A + BFABFAB011001010100FBAWeek 9b, Slide 5EECS42, Spring 2005 Prof. WhiteVDD/RDVDDNMOS Inverter (“NOT” Gate)vDSiD0vOUTvIN0VDDRD+vDS= vOUT–iD+vIN–VDDRD+vDS= vOUT–iD+vIN–Circuit:Voltage-Transfer CharacteristicVDDVT0110FAAFincreasingvGS= vIN> VTvGS= vin≤ VT vIN= VDDVDDWeek 9b, Slide 6EECS42, Spring 2005 Prof. WhiteNoise MarginsDefinition of Noise MarginsDefinition of Input LevelslogicswingVswVOHVOLOLILLIHOHHVVNMVVNM−=−=Noise margin highNoise margin lowWeek 9b, Slide 7EECS42, Spring 2005 Prof. WhiteNMOS NAND Gate• Output is low only if both inputs are highVDDRDABF011101110100FBATruth TableWeek 9b, Slide 8EECS42, Spring 2005 Prof. WhiteNMOS NOR Gate• Output is low if either input is highVDDRDABF011001010100FBATruth TableWeek 9b, Slide 9EECS42, Spring 2005 Prof. WhiteDisadvantages of NMOS Logic Gates• Large values of RDare required in order to– achieve a low value of VOL– keep power consumption lowÆ Large resistors are needed, but these take up a lot of space.• One solution is to replace the resistor with an NMOSFET that is always on.Week 9b, Slide 10EECS42, Spring 2005 Prof. WhiteThe CMOS Inverter: Intuitive PerspectiveVDDRnVIN= VDDCIRCUITSWITCH MODELSVDDRpVIN= 0 VVOUTVOUTVOL= 0 V VOH= VDDLow static power consumption, sinceone MOSFET is always off in steady stateVDDVINVOUTSDGGSDWeek 9b, Slide 11EECS42, Spring 2005 Prof. WhiteCMOS Inverter Voltage Transfer CharacteristicVINVOUTVDDVDD00N: offP: linN: linP: offN: linP: satN: satP: linN: satP: satVDDVINVOUTSDGGSDVDDVINVOUTVDDVINVOUTSDGGSDABDECWeek 9b, Slide 12EECS42, Spring 2005 Prof. WhiteN-Channel MOSFET P-Channel MOSFETWeek 9b, Slide 13EECS42, Spring 2005 Prof. WhiteCMOS Inverter Load-Line AnalysisVOUT=VDSnIDn=-IDp0VDDVINVOUTVDDVINVOUTIDn=-IDp–VGSp=VIN-VDD+VIN = VDD + VGSpincreasingVINincreasingVINVIN = 0 VVIN = VDDVDDVOUT = VDD + VDSpVDSp= 0VDSp= - VDD–VDSp=VOUT-VDD+0Week 9b, Slide 14EECS42, Spring 2005 Prof. WhiteVOUT=VDSnIDn=-IDp0VDD0CMOS Inverter Load-Line Analysis: Region AVDDVINVOUTVDDVINVOUTIDn=-IDp–VGSp=VIN-VDD+–VDSp=VOUT-VDD+VIN ≤ VTnWeek 9b, Slide 15EECS42, Spring 2005 Prof. WhiteVOUT=VDSnIDn=-IDp0VDD0CMOS Inverter Load-Line Analysis: Region BVDDVINVOUTVDDVINVOUTIDn=-IDp–VGSp=VIN-VDD+–VDSp=VOUT-VDD+VDD/2 > VIN > VTnWeek 9b, Slide 16EECS42, Spring 2005 Prof. WhiteVOUT=VDSnIDn=-IDp0VDD0CMOS Inverter Load-Line Analysis: Region DVDDVINVOUTVDDVINVOUTIDn=-IDp–VGSp=VIN-VDD+–VDSp=VOUT-VDD+VDD–|VTp| > VIN > VDD/2Week 9b, Slide 17EECS42, Spring 2005 Prof. WhiteVOUT=VDSnIDn=-IDp0VDD0CMOS Inverter Load-Line Analysis: Region EVDDVINVOUTVDDVINVOUTIDn=-IDp–VGSp=VIN-VDD+–VDSp=VOUT-VDD+VIN > VDD–|VTp|Week 9b, Slide 18EECS42, Spring 2005 Prof. WhiteThe CMOS Inverter: Current Flow during SwitchingVINVOUTVDDVDD00N: offP: linN: linP: offN: linP: satN: satP: linN: satP:
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