1Copyright 2001, Regents of University of CaliforniaLecture 17: 04/02/03 A.R. NeureutherVersion Date 03/30/03EECS 42 Intro. electronics for CS Spring 2003EECS 42 Introduction to Electronics for Computer ScienceAndrew R. NeureutherLecture # 17 Logic with Complementary DevicesS&O pp. 607-611 (read for graphs and not physics or equations), plus Handout of Wed Lectures. A)Discovering a Pull-Up Device B) Designing a Pull-Up DeviceC) EE 42 Pull-Up Device Model (42S_PMOS)D) Composite IOUTvs. VOUTE) Voltage Transfer Function and VMIDhttp://inst.EECS.Berkeley.EDU/~ee42/Copyright 2001, Regents of University of CaliforniaLecture 17: 04/02/03 A.R. NeureutherVersion Date 03/30/03EECS 42 Intro. electronics for CS Spring 2003Game Plan 04/02/03Monday 03/31/04R Welcome back plus HW#8 coachingR State Dependent Devices (Transistors)R Load Line, VTC, Pull Down Device (42S_NMOS)Wednesday 04/02/03:R Pull-Up Device (42S_PMOS)R VTC and VMIDNext (11th) Week:R Monday: 4/7/03 Logic Dynamic via Switched ResistorR Wednesday: 4/09/03 Quiz on dependent sources; then new material on Complementary GatesProblem set #9: Monday 3/31 and due at 2:30 4/09 in box in 240 Cory –Static Analysis of an Inverter with simplified EE 42 Device ModelsCopyright 2001, Regents of University of CaliforniaLecture 17: 04/02/03 A.R. NeureutherVersion Date 03/30/03EECS 42 Intro. electronics for CS Spring 2003Composite Current Plot for the 42S_NMOS Circuit with 200kΩ Load to GroundVIN=0 & 1VOUT(V)035IOUT(µA)2060100VIN = 3VIN= 5VTHEVENIN (Open Load)INORTON (Open Load)VTHEVENIN (200KΩ Load) = 3. 3 VINORTON (200KΩ Load)VOUTIOUTOutputVINVDDRPULL UPRLOAD(200KΩ)Problem #1Current when VOUTLowProblem #2Poor VOUTHigh with LoadCopyright 2001, Regents of University of CaliforniaLecture 17: 04/02/03 A.R. NeureutherVersion Date 03/30/03EECS 42 Intro. electronics for CS Spring 2003Problems and Opportunities in Logic Circuit DesignProblem #1: Significant wasted current and power when VOUTis low.Problem #2: High value of VOUTis adversely affected by a load resistor.Missed Opportunity: The value of the input control signal is not used to adjust the state of the pull-up device.What if : If the pull-up device could be a state-dependent device what kind of device would we want?Copyright 2001, Regents of University of CaliforniaLecture 17: 04/02/03 A.R. NeureutherVersion Date 03/30/03EECS 42 Intro. electronics for CS Spring 2003Pull-Up Device Design: Trial 1VOUT(V)035VIN=0 & 1IOUT(µA)2060100VIN = 3VIN= 5VIN = 3VIN=0 & 1VIN=5Problem #1 is worse!There is even more wasted current and power than before when VOUTis low because both devices are on at the same time.Look for a more Complementary approach.Similar pull-up and pull-down statesCopyright 2001, Regents of University of CaliforniaLecture 17: 04/02/03 A.R. NeureutherVersion Date 03/30/03EECS 42 Intro. electronics for CS Spring 2003Pull-Up Device Design: Trial 2VOUT(V)035VIN= 0 & 1IOUT(µA)2060100VIN = 3State 1VIN = 3VIN=5VIN=0Complementary pull-up and pull-down statesProblem #1 is solved.There is essentially no wasted current or power when VOUTis low.Note that in the pull-down case the current increases with the state number and in the pull-up case it decreases.2Copyright 2001, Regents of University of CaliforniaLecture 17: 04/02/03 A.R. NeureutherVersion Date 03/30/03EECS 42 Intro. electronics for CS Spring 2003Input for State Control SignalPull-Down and Pull-Up Must Complement Rather Than Fight Each OtherInput for State Control SignalShare Same SignalReduce the Short-Circuit Current by making either one or the other device off.Pull-DownVOUTIOUTOutputVINVDDPull-UpVINDischarging CurrentCharging CurrentCopyright 2001, Regents of University of CaliforniaLecture 17: 04/02/03 A.R. NeureutherVersion Date 03/30/03EECS 42 Intro. electronics for CS Spring 2003Desirable Complementary Device CharacteristicsVDDVOUTIOUTOutputVINWe desire characteristics that are complementary for the pull-down and pull-up state-dependent devices.Low not leakHighCharge OutputPull-Up CurrentHigh Discharge OutputLow not leakPull-DownCurrentHighLowVINCopyright 2001, Regents of University of CaliforniaLecture 17: 04/02/03 A.R. NeureutherVersion Date 03/30/03EECS 42 Intro. electronics for CS Spring 2003Designing the Complementary DeviceMake ThisInto ThisVOUT(V)035VIN=0IOUT(µA)2060100VIN = 3VIN= 5VOUT(V)035VIN= 5IOUT(µA)2060100VIN = 3VIN=0 The creation of current with input State (VIN) is reverse ordered (and also shifted).The dependence on VOUT is reverse ordered and shifted by VDDThe curve sets are very similar but have two key changes.Copyright 2001, Regents of University of CaliforniaLecture 17: 04/02/03 A.R. NeureutherVersion Date 03/30/03EECS 42 Intro. electronics for CS Spring 2003VDD-VXGives Complementary CharacteristicsV’OUT = VDD-VOUTPull-DownIOUTOutputVINVDDPull-UpVINV’IN = VDD-VINV’IN = VDD-VINV’OUT = VDD-VOUTPhysical Interpretation as device related rather than logic circuit related voltages. ReverseShiftCopyright 2001, Regents of University of CaliforniaLecture 17: 04/02/03 A.R. NeureutherVersion Date 03/30/03EECS 42 Intro. electronics for CS Spring 2003Saturation Current NMOS ModelCurrent IOUTonly flows when VINis larger than the threshold value VTDand the current is proportional to VOUTup to VOUT-SAT-Dwhere it reaches the saturation current()DSATOUTTDINDDSATOUTVVVkI−−−−−=VOUT(V)IOUT(µA)0352060100State 3 VIN= 3VLinear (with VOUT)Saturation (with VOUT)Example:kD= 25 µA/V2VTD= 1VVOUT-SAT-D= 1V()AVVVVAIPDSATOUTµµ50113252=−=−−Note that we have added an extra parameter to distinguish between threshold (VTD) and saturation (VOUT-SAT-D).Use these values in the homework.Copyright 2001, Regents of University of CaliforniaLecture 17: 04/02/03 A.R. NeureutherVersion Date 03/30/03EECS 42 Intro. electronics for CS Spring 2003Saturation Current 42S_PMOS ModelCurrent IOUTonly flows when VINis smaller than VDD minus the threshold value VTUand the current is proportional to (VDD-VOUT) up to (VDD-VOUT-SAT-U) where it reaches the saturation current()USATOUTTUINDDUUSATOUTVVVVkI−−−−−−=Example:kU= 20 µA/V2VTU= 1VVOUT-SAT-U= 1V()AVVVVAIUSATOUTµµ201135202=−−=−−Linear (with VOUT)VOUT(V)IOUT(µA)0352060100State 3 VIN= 3VSaturation (with VOUT)Use these values in the homework.3Copyright 2001, Regents of University of CaliforniaLecture 17: 04/02/03 A.R. NeureutherVersion Date 03/30/03EECS 42 Intro. electronics for CS Spring 200342S_PMOS Pull-UP
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