Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 6: 9/24/01 A.R. NeureutherVersion Date 9/23/01Lecture 8: September 24th, 2001Nodal AnalysisA)Review of KCL and KVLB) Nodal Analysis StrategyC)Special Situations and ExamplesD)Accounting for All UnknownsReading: Schwarz and Oldham 2.3 pp. 53-58The following slides were derived from those prepared by Professor Oldham For EE 40 in Fall 0120 min Quiz on HW 1-4 at start of class on Wed. 9/26Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 6: 9/24/01 A.R. NeureutherVersion Date 9/23/01BRANCHES AND NODESCircuit with several branches connected at a node: branch (circuit element)3i2i4i1i(Sum of currents entering node) − (Sum of currents leaving node) = 0q = charge stored at node is zero. If charge is stored, for example in a capacitor, then the capacitor is a branch and the charge is stored there NOT at the node. KIRCHOFF’s CURRENT LAW “KCL”:Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 6: 9/24/01 A.R. NeureutherVersion Date 9/23/01Suppose imbalance in currents is 1µA = 1 µC/s (net current entering node)Assuming that q = 0 at t = 0, the charge increase is 10−6 C each second or charge carriers each second WHAT IF THE NET CURRENT WERE NOT ZERO?12196106106.1/10×=×−−But by definition, the capacitance of a node to ground is ZERO because we show any capacitance as an explicit circuit element (branch). Thus, the voltage would be infinite (Q = CV).Something has to give! In the limit of zero capacitance the accumulation of charge would result in infinite electric fields … there would be a spark as the air around the node broke down.Charge is transported around the circuit branches (even stored in some branches), but it doesn’t pile up at the nodes!Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 6: 9/24/01 A.R. NeureutherVersion Date 9/23/01KIRCHHOFF’S CURRENT LAW EXAMPLECurrents entering the node: 24 µACurrents leaving the node: −4 µA + 10 µA + i Three statements of KCLA 18i 0i10424 0iA 18i 0i10)4(24 0iA 18i i10424 iiALLALLIN OUToutinoutinµµµ=⇒=++−−==⇒=−−−−==⇒++−==∑∑∑∑EQUIVALENT i 10 µA 24 µA -4 µA24 = 10 + (−4) + ii = 18 µA}Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 6: 9/24/01 A.R. NeureutherVersion Date 9/23/01GENERALIZATION OF KCLSum of currents entering and leaving a closed surface is zeroPhysics 7BNote that circuit branches could be inside the surface.Could be a big chunk of circuit in here, e.g., could be a “Black Box”The surface can enclose more than one nodeCopyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 6: 9/24/01 A.R. NeureutherVersion Date 9/23/01KIRCHHOFF’S CURRENT LAW USING SURFACESExampleiA2A5=+∴µµentering leaving5 µA2 µAi = ?surfacei must be 50 mA50 mAi?Another examplei=7µACopyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 6: 9/24/01 A.R. NeureutherVersion Date 9/23/01Example of the use of KCLR1C1R2V1X+-At node X:Current into X from the left:(V1-vX)/R1Current out of X to the right:vX/R2 + CdvX/dtKCL:(V1-vX)/R1 = vX/R2 + CdvX/dtGiven V1, This differential equation can be solved for vX(t).Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 6: 9/24/01 A.R. NeureutherVersion Date 9/23/01BRANCH AND NODE VOLTAGESThe voltage across a circuit element is defined as the difference between the node voltages at its terminalsSpecifying node voltages: Use one node as the implicit reference(the “common” node … attach special symbol to label it)Now single subscripts can label voltages:e.g., vbmeans vb− ve, vameans va− ve, etc.cev2v1dab+−−+0ve≡(since it’s the reference)ad2vvv−=select as ref. ⇒ “ground”Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 6: 9/24/01 A.R. NeureutherVersion Date 9/23/01KIRCHHOFF’S VOLTAGE LAW (KVL)The algebraic sum of the “voltage drops” around any “closed loop” is zero.Voltage drop→ defined as the branch voltage if the + sign is encountered first; it is (-) the branch voltage if the − sign is encountered first … important bookkeepingWhy? We must return to the same potential (conservation of energy).+-V2Path“rise” or “step up”(negative drop)+-V1Path“drop”Closed loop: Path beginning and ending on the same nodeCopyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 6: 9/24/01 A.R. NeureutherVersion Date 9/23/01KVL EXAMPLEPath 1:0vvvb2a=++−↑va− vbYEP!Path 2:0vvvc3b=+−−Path 3:0vvvvc32a=+−+−vcva+−+−+ −vbv3v2+ −ref. node+-v2= va-vbv3= vc-vbNote that:Examples of Three closed paths:, , Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 6: 9/24/01 A.R. NeureutherVersion Date 9/23/01Example of the use of KVLVoltage drop across R1 (left to right):i R1Ldi/dtVoltage drop across L1 (top to bottom):Starting at the bottom and walking clockwise, summing voltage drops:-V1+ i R1 + Ldi/dt = 0Given V1, this differential equation can be solved for i(t).R1L1V1+−iCopyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 6: 9/24/01 A.R. NeureutherVersion Date 9/23/01HOW MANY NODE EQUATIONS DO WE NEED?The circuit is completely described by the voltage of each node and the current through each branch. Thus the number of unknowns = (NNODES–1) + NBRANCHESSince we already know the reference node voltage, we need NNODES –1 node equations.Write a node equation at each of the nodes except the reference node!cev2v1dab+−−+0ve≡(since it’s the reference)select as ref. ⇒ “ground”Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 6: 9/24/01 A.R. NeureutherVersion Date 9/23/01SAVE TIME IN SPECIAL CASES!cv2v1dab+−−+efvS+−Eliminate this trivial nodeby a single resistor REQ= R1+ R2R1R2Eliminate either Vb or Vcby using a surface that encloses the voltage source and the nodes at is terminals.This surfaces is a
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