1Copyright 2001, Regents of University of CaliforniaLecture 21: 04/21/03 A.R. NeureutherVersion Date 04/19/03EECS 42 Intro. electronics for CS Spring 2003EECS 42 Introduction to Electronics for Computer ScienceAndrew R. NeureutherLecture # 21 Clock Operation of LatchesHandout of Monday Lecture. A) 2ndMidterm ReturnedB) Latch circuit to hold/release signalsC) Cascade CMOS elements with latcheshttp://inst.EECS.Berkeley.EDU/~ee42/Copyright 2001, Regents of University of CaliforniaLecture 21: 04/21/03 A.R. NeureutherVersion Date 04/19/03EECS 42 Intro. electronics for CS Spring 2003Game Plan 04/21/03Last Week: Logic Delay; resistor model, CMOS operation and delayMonday 4/14/03:R 2ndMidterm returnedR CMOS Latch and use in logic cascadeWednesday 04/09/03:R Clocked Latch and Timing DiagramR Latency and ThroughputR Feedback in logic to produce memoryNext (13th) Week: Diodes and MOS DevicesProblem set #10 for 4/303: Logic Delay; Cascade; Latches and Clock frequencyCopyright 2001, Regents of University of CaliforniaLecture 21: 04/21/03 A.R. NeureutherVersion Date 04/19/03EECS 42 Intro. electronics for CS Spring 2003CMOS Logic Gate: Example InputsABCABCVDDVOUTNMOS B and C conduct; A openLogic is Complementary and produces F = 0A = 0B = 1C = 1PMOS A conducts; B and C OpenOutput is High= 0Copyright 2001, Regents of University of CaliforniaLecture 21: 04/21/03 A.R. NeureutherVersion Date 04/19/03EECS 42 Intro. electronics for CS Spring 2003Logic Gate Propagation Delay: Initial StateThe initial state depends on the old (previous) inputs.The equivalent resistance of the pull-down or pull-up network for the transient phase depends on the new (present) input state.ABCABCVDDVOUTRURURURDRDRDCOUT= 50 fFExample: A=0, B=0, C=0 for a long time.These inputs provided a path to VDD for a long time and the capacitor has precharged up to VDD= 5V.Copyright 2001, Regents of University of CaliforniaLecture 21: 04/21/03 A.R. NeureutherVersion Date 04/19/03EECS 42 Intro. electronics for CS Spring 2003Logic Gate: Worst Case ScenariosWhat combination of previous and present logic inputs will make the Pull-Down the fastest?What combination of previous and present logic inputs will make the Pull-Down the slowest?What combination of previous and present logic inputs will make the Pull-Up the fastest?What combination of previous and present logic inputs will make the Pull-Up the slowest?Fastest overall?Slowest overall?ABCABCVDDVOUTRURURURDRDRDCOUT= 50 fFCopyright 2001, Regents of University of CaliforniaLecture 21: 04/21/03 A.R. NeureutherVersion Date 04/19/03EECS 42 Intro. electronics for CS Spring 2003Logic Gate CascadeTo avoid large resistance due to many gates in series, logic functions with 4 or more inputs are usually made from cascading two or more 2-4 input blocks.B2 = VOUT 1The four independent input are A1, B1, A2 and C2.A2 high discharges gate 2 without even waiting for the output of gate 1.C2 high and A2 low makes gate 2 wait for Gate 1 outputA2B2VDDA1B1A1B1VDDVOUT 1B2C2A2C2VOUT 250 fF50 fF2Copyright 2001, Regents of University of CaliforniaLecture 21: 04/21/03 A.R. NeureutherVersion Date 04/19/03EECS 42 Intro. electronics for CS Spring 2003Data Synchronization problem• Combinatorial logic gates can give incorrect answers prematurely and may take several gate propagation delays produce an answer.• Clocks (signals as to when to proceed) and latches (which capture and hold the correct outputs) can provide synchronization.Copyright 2001, Regents of University of CaliforniaLecture 21: 04/21/03 A.R. NeureutherVersion Date 04/19/03EECS 42 Intro. electronics for CS Spring 2003Latch Controlled by a ClockAn inverter with clocked devices in series can form a latch.When the clock φ is high its complement φ is low and the inverter operates.To synchronize the data the clock remains low until the data is correct at all locations on the chip. When the clock goes high the inverse of the data is passed.COUT VDDVOUT φφVINCopyright 2001, Regents of University of CaliforniaLecture 21: 04/21/03 A.R. NeureutherVersion Date 04/19/03EECS 42 Intro. electronics for CS Spring 2003Clock Signal DefinitionsPeriod0timeClock1Rising-edgePτHIGHτLOWPeriod =P = τHIGH+ τLOWDuty Cycle = (τHIGH)/(τHIGH+ τLOW)Frequency = 1/P = 1/(τHIGH+ τLOW)Falling-edgeCopyright 2001, Regents of University of CaliforniaLecture 21: 04/21/03 A.R. NeureutherVersion Date 04/19/03EECS 42 Intro. electronics for CS Spring 2003Latch Work Best In PairsThe second stage operates while the clock is high and inverts the signal on CL1to charge or discharge CL2and downstream logic gate inputs.VDDVOUT_EXTVDDVOUT_INTφφφφCL1CL2VINThe first stage operates while the clock is low and inverts and amplifies the arriving signal and charges or discharges CL1.timeClock10Copyright 2001, Regents of University of CaliforniaLecture 21: 04/21/03 A.R. NeureutherVersion Date 04/19/03EECS 42 Intro. electronics for CS Spring 2003A Double Latch is an Edge-Triggered D Type Flip-FlopVDDVOUT VDDVOUT φφφφCL1CL2VINDuring the low part of the clock cycle this circuit records the input value and when the clock goes high drives VOUT 2 to the voltage level that arrived. (This is the classic function of a D flip-flop.)Note that this circuit is not fooled by noise on the input and makes its decision on the rising edge of the clock (edge-triggered).Copyright 2001, Regents of University of CaliforniaLecture 21: 04/21/03 A.R. NeureutherVersion Date 04/19/03EECS 42 Intro. electronics for CS Spring 2003Example of Circuits to Integrate with LatchesA1B1A1VDDVOUT-C2Gate 1CG1B1A2B2C2A2C1B2VDDVOUT-C1Gate 2CG23Copyright 2001, Regents of University of CaliforniaLecture 21: 04/21/03 A.R. NeureutherVersion Date 04/19/03EECS 42 Intro. electronics for CS Spring 2003Latch Implementation: LumpedA1B1A1VDDVOUT-C2Gate 1CG1B1A2B2C2A2C1B2VDDVOUT-C1Gate 2CG2VDDVOUT-L0VDDVMID-L0 φφφφCL1CL2VIN-L0VDDVOUT-L0VDDVMID-L0 φφφφCL1CL2VIN-L0Latch 0Latch 1Copyright 2001, Regents of University of CaliforniaLecture 21: 04/21/03 A.R. NeureutherVersion Date 04/19/03EECS 42 Intro. electronics for CS Spring 2003Latch Operation: LumpedA1B1A1VDDVOUT-C2CG1B1A2B2C2A2C1B2VDDVOUT-C1CG2VDDVOUT-L0VDDVMID-L0 φφφφCL1CL2VIN-L0VDDVOUT-L0VDDVMID-L0 φφφφCL1CL2VIN-L0Latch 0Latch 1timeClock10LowLowHighHighGate 1Gate 2τHIGH= τL_EXT+ τGATE1+ τGATE2τLOW= τL_INTCopyright 2001, Regents of University of CaliforniaLecture 21: 04/21/03 A.R. NeureutherVersion Date 04/19/03EECS 42
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