1Copyright 2003, Regents of University of CaliforniaEECS 42 Intro. Digital Electronics, Fall 2003 Lecture 26: 12/04/03 A.R. NeureutherVersion Date 11/30/03Review for the Final ExamTransients*Logic Functions and Timing DiagramsCircuit Analysis with dependent SourcesOp-Amps*Load Line and Static Analysis of Logic GatesCMOS Logic Functions, Delay, LatchesDiode Circuit Analysis, Voltage Controlled RSee Web Site under Exams for Coverage, Review Sessions and Office HoursLikely 7 ProblemsMidterm Bonus = 2/3 best +1/3 worst* Possible Bonus = 2/3 best +1/3 worstCopyright 2003, Regents of University of CaliforniaEECS 42 Intro. Digital Electronics, Fall 2003 Lecture 26: 12/04/03 A.R. NeureutherVersion Date 11/30/03RVoutVCo0=+−5VRC1µsec=CPULSE: Output is Rising exponential then Falling exponentialExample: Switch rises at t =0, falls at t = 0.1, 1 or 10µsec (Do 1µsec case)Solution: for RC = 1µsec: during the first rise V obeys:0123456012345time (microseconds)Vout610te1[5V−−−=]Now starting at 1µsec we aredischarging the capacitor so the form is a falling exponential withinitial value 3.16 V:Thus at t = 1µsec, rising voltage reaches]e1[5=−-13.16VWhat is equation?Lecture 72Copyright 2003, Regents of University of CaliforniaEECS 42 Intro. Digital Electronics, Fall 2003 Lecture 26: 12/04/03 A.R. NeureutherVersion Date 11/30/03How to Combine Gate to Produce a Desired Logic Function?(More basic Logical Synthesis)Example:01111011010100011010C010010100000FBAF= C +ABB ACABCABCFCopyright 2003, Regents of University of CaliforniaEECS 42 Intro. Digital Electronics, Fall 2003 Lecture 26: 12/04/03 A.R. NeureutherVersion Date 11/30/03Logical SynthesisGuided by DeMorgan’s TheoremDeMorgan’s Theorem :[] C B A CBA=++or[] C BA CBA =++Example of Using DeMorgan’s Theorem:Thus any sum of products expression can be immediately synthesized from NAND gates aloneCDEAB EDC BA F•=••+•=ABCDFE3Copyright 2003, Regents of University of CaliforniaEECS 42 Intro. Digital Electronics, Fall 2003 Lecture 26: 12/04/03 A.R. NeureutherVersion Date 11/30/03C,B,AD)BA( +)(__CB⋅BDtttttLogic stateτττ2τ2τ03ττTIMING DIAGRAMSShow transitions of variables vs timeABCNote that becomes valid two gate delays after B&C switch, because the invert function takes one delay and the NAND function a second.)(__CB⋅No change at t =3τNote becomes valid one gate delay after B switchesB10Copyright 2003, Regents of University of CaliforniaEECS 42 Intro. Digital Electronics, Fall 2003 Lecture 26: 12/04/03 A.R. NeureutherVersion Date 11/30/03Feedback Can Provide MemoryQQHHLLHHLecture 194Copyright 2003, Regents of University of CaliforniaEECS 42 Intro. Digital Electronics, Fall 2003 Lecture 26: 12/04/03 A.R. NeureutherVersion Date 11/30/03EXAMPLE WITH BOTH SPECIAL CASES+_I1R4R1R2R3V2abcd()0423211=+−+−−RVVRRVRVIaaaLecture 8Copyright 2003, Regents of University of CaliforniaEECS 42 Intro. Digital Electronics, Fall 2003 Lecture 26: 12/04/03 A.R. NeureutherVersion Date 11/30/03GmVcdVoltage-controlled current source … I = GmVcdAiIcCurrent-controlled current source … I = AiIc+-RmIcCurrent-controlled voltage source … V = Rm IcThe 4 Basic Linear Dependent SourcesVoltage-controlled voltage source … V = AvVcdAvVcd+-Parameter being sensedConstant of proportionalityOutputLecture 135Copyright 2003, Regents of University of CaliforniaEECS 42 Intro. Digital Electronics, Fall 2003 Lecture 26: 12/04/03 A.R. NeureutherVersion Date 11/30/03EXAMPLE CIRCUIT: INCREASED OUTPUT RESISTANCERIN v = 0 vIN + - + - GmvIN + - vTEST RO iTEST RE vE Add resistor REAnalysis: apply iTESTand evaluate vTESTUnknowns: iTEST, vTEST, vIN, vENeed 3 equations to find the ratio of iTEST/ vTESTvIN= -vE and is not zero!KCL at vEKVL at vOUTIntuitive Explanation: GmVINburps currentwhich has to also go through R0. This raises vTESTand the output impedance vTEST/iTESTThe input has been assumed to be shortedTry a bag. It is even easierFinish this in the homeworkCopyright 2003, Regents of University of CaliforniaEECS 42 Intro. Digital Electronics, Fall 2003 Lecture 26: 12/04/03 A.R. NeureutherVersion Date 11/30/03CASCADE OP-AMP CIRCUITSV1+−V3V2RFR1R2R3V0+−1K9KIINHow do you get started on finding VO?Hint: IINdoes not affect VO1See the further examples of op-amp circuits in the readerHint: Identify Stages6Copyright 2003, Regents of University of CaliforniaEECS 42 Intro. Digital Electronics, Fall 2003 Lecture 26: 12/04/03 A.R. NeureutherVersion Date 11/30/03Saturation Current NMOS ModelCurrent IOUTonly flows when VINis larger than the threshold value VTDand the current is proportional to VOUTup to VOUT-SAT-Dwhere it reaches the saturation current()DSATOUTTDINDDSATOUTVVVkI−−−−−=VOUT(V)IOUT(µA)0352060100State 3 VIN= 3VLinear (with VOUT)Saturation (with VOUT)Example:kD= 25 µA/V2VTD= 1VVOUT-SAT-D= 1V()AVVVVAIPDSATOUTµµ50113252=−=−−Note that we have added an extra parameter to distinguish between threshold (VTD) and saturation (VOUT-SAT-D).Use these values in the homework.Lecture 17Copyright 2003, Regents of
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