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Berkeley ELENG 42 - Transistors, digital

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PowerPoint PresentationReview SessionFinal ExamMOS transistor Below thresholdNMOS in the linear (Triode) regionNMOS with increasing VdsSaturationSlide 8Basic CMOS InverterSlide 10NMOS TransistorNMOS I-V CharacteristicNMOS I-V CurvesSaturation in a MOS transistorSlide 15Logic GatesTransistor Inverter ExampleComplementary NetworksSlide 19Evaluation of Logical Expressions with “Truth Tables”Slide 21Slide 22Slide 23NAND Gate Pull-Up Model*Slide 25Slide 26Slide 27Definition of FanoutClocked logicEdge triggerSequential logic12/10/2004 EE 42 fall 2004 lecture 42 1Lecture #42: Transistors, digital•This week we will be reviewing the material learned during the course•Today: review–CMOS transistors –Digital logic12/10/2004 EE 42 fall 2004 lecture 42 2Review Session•When: Thursday, Dec. 16th; 3-6pm•Where: Evans 0009•Format: Open, bring questions12/10/2004 EE 42 fall 2004 lecture 42 3Final ExamDate/Time: •SATURDAY, DECEMBER 18, 2004 •5-8PMLocation: 150 GSPP(Goldman School of Public Policy) Format:•Closed book•One page, (two sides) of notes12/10/2004 EE 42 fall 2004 lecture 42 4nPoxide insulatorndrain- +sourcegateMOS transistorBelow thresholdVGS < VtBelow threshold, there are no electrons under the gate oxide, and the holes in the substrate are blocked from carrying current by reverse biased diode junctions12/10/2004 EE 42 fall 2004 lecture 42 5nPoxide insulatorndrain- +sourcegateNMOS in the linear (Triode) regionVGS > VtIf the gate voltage is above threshold, but the source to drain voltage is small, the charge under the gate is uniform, and carries current much like a resistorThe electrons move under the influence of theElectric field at a velocity: ν=μE where E=volts/distanceAnd they must travel a distance L to cross the gateSince the total charge is Q=CVgs, we will have a current Id=μCgateVds (Vgs-Vth)/L2= μ(εox/dox)Vds (Vgs-Vth)W/L12/10/2004 EE 42 fall 2004 lecture 42 6nPoxide insulatorndrain- +sourcegateNMOS with increasing VdsVGS > VtAs the voltage from the source to the drain is increased, the current increases, but not by as much because the charge is attracted out from under the oxide, beginning to pinch off the channel12/10/2004 EE 42 fall 2004 lecture 42 7Saturation•As the Source-Drain voltage is increased, there will be a significant change in the charge at different distances along the gate•When the voltage across the device at the drain end goes below threshold, the current is pinched off.•If there is no current out the drain end, however, the current due to the carriers which are available from the source cause the voltage to be closer to that of the source.•These two effects cause a small region to form near the drain which limits the current. This is called saturation12/10/2004 EE 42 fall 2004 lecture 42 8A little more MOS “Theory”We have two regions: the resistive region at smaller VDS and the saturation region at higher VDS .IDVDSVGSIn the resistive region we start out like a simple resistor between source and drain (whose value depends on gate voltage) and gradually the curve “bends over” as we approach saturationIn the saturation we have a small gradual increase of I with VDS VGSSGVDSiD++-D12/10/2004 EE 42 fall 2004 lecture 42 9Basic CMOS InverterInverterINOUTVDDp-chVDDOUTINn-chCMOS InverterGROUNDINOUTVDDN-WELLNMOS GatePMOS GateAl “wires”GROUNDINOUTVDDN-WELLNMOS GatePMOS GateAl “wires”Example layout of CMOS Inverter12/10/2004 EE 42 fall 2004 lecture 42 10GROUNDIN OUTVDDN-WELLNMOS GatePMOS GateAl “wires”12/10/2004 EE 42 fall 2004 lecture 42 11n-typemetalmetaloxide insulatormetalp-typemetalgatesourcedrainn-type-+VGS-+VDSIDIGGDSIDIG- VDS ++VGS_NMOS Transistor12/10/2004 EE 42 fall 2004 lecture 42 12GDSIDIG- VDS ++VGS_NMOS I-V Characteristic•Since the transistor is a 3-terminal device, there is no single I-V characteristic.•Note that because of the insulator, IG = 0 A.•We typically define the MOS I-V characteristic asID vs. VDS for a fixed VGS. •The I-V characteristic changes as VGS changes.12/10/2004 EE 42 fall 2004 lecture 42 13triode modecutoff mode (when VGS < VTH(N))saturation modeVDSIDVGS = 3 VVGS = 2 VVGS = 1 VVDS = VGS - VTH(n)NMOS I-V Curves12/10/2004 EE 42 fall 2004 lecture 42 14Saturation in a MOS transistor•At low Source to drain voltages, a MOS transistor looks like a resistor which is “turned on” by the gate voltage•If a more voltage is applied to the drain to pull more current through, the amount of current which flows stops increasing→ an effect called p inch-o ff.•Think of water being sucked through a flexible wall tube. Dropping the pressure at the end in order to try to get more water to come through just collapses the tube. •The current flow then just depends on the flow at the input: VGS•This is often the desired operating range for a MOS transistor (in a linear circuit), as it gives a current source at the drain as a function of the voltage from the gate to the source.12/10/2004 EE 42 fall 2004 lecture 42 15NAND gateA BA B A BMaking a NAND gate: (NMOS pulls “down”, PMOS “up”)NMOS portion: both inputs need to be high for output to be low  seriesCMOS DIGITAL LOGIC0 0 0 10 1 0 11 0 0 11 1 1 0PMOS portion: either input can be low for output to be high  parallelC=BCAVDD12/10/2004 EE 42 fall 2004 lecture 42 16These are circuits that accomplish a given logic function such as “OR”. We will shortly see how such circuits are constructed. Each of the basic logic gates has a unique symbol, and there are several additional logic gates that are regarded as important enough to have their own symbol. The set is: AND, OR, NOT, NAND, NOR, and EXCLUSIVE OR.Logic GatesABC=A·BANDC = ABNANDBAC = NORABBANOTAAORABC=A+BEXCLUSIVE ORABBAC 12/10/2004 EE 42 fall 2004 lecture 42 17Transistor Inverter ExampleIt may be simpler to just think of PMOS and NMOS transistors instead of a general 3 terminal pull-up or pull-down devices or networks.VIN-DPull-Down NetworkVOUTIOUTOutputVDDPull-Up NetworkVIN-UVIN-DVIN-UVOUTIOUTOutputVDDp-type MOSTransistor(PMOS)n-type MOSTransistor(NMOS)12/10/2004 EE 42 fall 2004 lecture 42 18Complementary Networks•If inputs A and B are connected to parallel NMOS, A and B must be connected to series PMOS.•The reverse is also true.•Determining the logic function from CMOS circuit is not hard:–Look


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Berkeley ELENG 42 - Transistors, digital

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Lecture 2

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Lecture 3

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