Lecture 13Sequential SwitchingPulse DistortionExampleSlide 5Slide 6Slide 7Design IssuesPropagation DelayIllustrationSlide 11Graphing Propagation through Multiple Logic GatesLogic GatesSlide 14Logic Functions: Truth TablesSlide 16Timing DiagramsStrategy for Timing DiagramsSlide 19Slide 20Lecture 13Today we willExamine how the logic gate model (RC circuit) reacts to a sequence of input changesRelate these results to clocking speedDefine propagation delayIntroduce digital logic gatesExamine how signals propagate through logic circuitstimeVin0timeVin0VouttimeVin0VoutSequential SwitchingWhat if we step up the input to a logic circuit,wait for the output to respond,then bring the input back down to perform the next computation?We need to wait for the output to reach a recognizable logic level, before changing the input again.This affects clock speed.Pulse Distortion01234560 1 2 3 4 5TimeVin, VoutPulse width = RC+Vout(t)–RVin(t) +C01234560 5 10 15 20 25TimePulse width = 10RCVin, VoutExampleSuppose that the capacitor is discharged at t=0.With Vin(t) as shown, find Vout(t).+Vout(t)–Vin(t) +1 nF2.5 k4 V5 sVin(t)tExampleFirst, Vout(t) will approach 4 V exponentially. We write the equation for this part using:Initial condition Vout(0) = 0 VFinal value Vout,f = 4 VTime constant RC = (2.5 k)(1 nF) = 2.5 sVout(t) = Vout,f + (Vout(0)-Vout,f)e-t/RC Vout(t) = 4-4e-t/2.5s V for 0 ≤ t ≤ 5 sExampleThen, at 5 s, Vout(t) will approach 0 V exponentially. We write the equation for this part using:Initial condition Vout(5 s) = ? Use equation from previous step, since Vout is continuous. Vout(5s) = 4-4e-5s/2.5s = 3.44 VFinal value Vout,f = 0 VTime constant RC = (2.5 k)(1 nF) = 2.5 sVout(t) = Vout,f + (Vout(t0) -Vout,f)e-(t-t0)/RCVout(t) = 3.44e-(t-5s)/2.5s for t > 5 s00.511.522.533.540 2 4 6 8 10Vout(t) =4-4e-t/2.5s for 0 ≤ t ≤ 5 s3.44e-(t-5s)/2.5s for t > 5 s{ExampleVin(t)Vout(t)t (s)Design IssuesHow long between successive inputs?Need output to reach recognizable logic levelOutput must be at this level long enough to serve asinput to next logic gateHow many consecutive logic gates does signal gothrough before being “cleaned up” or saved in staticmemory cell?Eventually the signal gets really badBut adding hardware adds cost and delayPropagation DelaySuppose an input goes from some initial voltage to some final voltage.In our examples, the input switch is immediate, but in practice it is not.Propagation delay is officially defined as:(time when output is halfway to final value) minus (time when input is halfway to final value)IllustrationUsing our equation for Vout(t), we can find:tP,LH (time when Vout(t) = 2 V, as it goes from 0 V to 4 V) – 0 stP,HL (time when Vout(t) = 1.72 V, as it goes from 3.44 V to 0 V) – 5 s00.511.522.533.540 2 4 6 8 10tP,HLtP,LHtP,HL = tP,LH = 1.725 sPropagation DelayIt’s not a coincidence that the propagation delays were the same.For a general RC circuit that has an input voltage switch at t = t0,Vout(t) = Vout,f + (Vout(t0) -Vout,f)e-(t-t0)/RCThe time when Vout(t) is ½ (Vout,f + Vout(t0)) is given by ½ (Vout,f + Vout(t0)) = Vout,f + (Vout(t0) -Vout,f)e-(t-t0)/RCSimplifying,½ = e-(t-t0)/RCt = (ln 2)(RC) + t0The propagation delay, the difference between this time and t0, istP = (ln 2)(RC) Depends only on time constant!Graphing Propagation through Multiple Logic GatesWe will want to examine how these RC-related delays affect a signal going through multiple logic gates.The math involved in putting an RC output (decaying exponential) into another RC circuit is not so easy.So, when analyzing a circuit with many logic gates, we will use the following simplification:Logic Gate0tVtPtV→→Logic GatesWe have been using a simple RC circuit to model a logic gate.In each case, the final value of Vout was Vin.This will not always be true; sometimes, the output will go to logic 0 when the input is logic 1 and vice-versa.To determine what the final value of a logic gate output will be, we need to learn the types of logic gates.Logic GatesABC=A·BANDC = ABNANDBANORABBA AAORABC=A+B(EXCLUSIVE OR)ABBAC NOTXORLogic Functions: Truth TablesWe specify what a logic circuit does by listing the output for each possible input. This listing is called a truth table.A A0 11 0NOTA B A·B A·B0 0 0 10 1 0 11 0 0 11 1 1 0AND NANDLogic Functions: Truth TablesA B A+B A+B0 0 0 10 1 1 01 0 1 01 1 1 0 OR NORA BA B A B0 0 0 10 1 1 01 0 1 01 1 0 1XOR XNORTiming DiagramsNow let’s look at how signals propagate through logic gates, taking delay into consideration.Sketch the output for each logic gate in a more complicated circuit.ABA(A)·Bt10A, Bt10AtPt10tP(A)·B2tPInvalid info!Strategy for Timing DiagramsTo find the output for a particular gate,Graph the inputs for that gateGraph the result of the logic gate using the input graphsShift right by one tPExampleDABCt10A, B,
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