1Copyright 2001, Regents of University of CaliforniaLecture 20: 04/14/03 A.R. NeureutherVersion Date 04/05/03EECS 42 Intro. electronics for CS Spring 2003EECS 42 Introduction to Electronics for Computer ScienceAndrew R. NeureutherLecture # 20 Logic TransientsHandout of Monday Lecture. A) 2ndMidterm Review (Cont.)B) Latch circuit to hold/release signalsC) Cascade CMOS elements with latchesD)Logic Feedback creates memoryhttp://inst.EECS.Berkeley.EDU/~ee42/Copyright 2001, Regents of University of CaliforniaLecture 20: 04/14/03 A.R. NeureutherVersion Date 04/05/03EECS 42 Intro. electronics for CS Spring 2003Game Plan 04/14/03Last Week: Logic Delay; resistor model, CMOS operation and delayMonday 4/14/03:R 2ndMidterm review (Cont.)R CMOS Latch and use in logic cascadeR Feedback in logic to produce memoryWednesday 04/09/03:R 2ndMidtermNext (13th) Week: Diodes and MOS OperationNo Problem set for 4/16 as Midterm 4/16: Lectures 1-17 with emphasis on Lectures 10-17; Review Session Monday 5:30-7PMProblem set #10 for 4/23: Logic Delay2Copyright 2001, Regents of University of CaliforniaLecture 20: 04/14/03 A.R. NeureutherVersion Date 04/05/03EECS 42 Intro. electronics for CS Spring 2003Composite Current Plot for the 42S_NMOSCircuit with 200kΩ Load to GroundVIN= 0 & 1VOUT(V)035IOUT(µA)2060100VIN = 3VIN= 5VTHEVENIN (Open Load)INORTON (Open Load)VTHEVENIN (200KΩ Load) = 3. 3 VINORTON (200KΩ Load)VOUTIOUTOutputVINVDDRPULL UPRLOAD(200KΩ)Copyright 2001, Regents of University of CaliforniaLecture 20: 04/14/03 A.R. NeureutherVersion Date 04/05/03EECS 42 Intro. electronics for CS Spring 2003Voltage Transfer Function for the 42S_NMOS Logic Circuit w/wo LoadVOUT(V)VIN(V)035350VIN= 0 & 1VIN = 3VIN= 5Open Load200 KΩ LoadComplete this VTC for the 42PD device in the Homework3Copyright 2001, Regents of University of CaliforniaLecture 20: 04/14/03 A.R. NeureutherVersion Date 04/05/03EECS 42 Intro. electronics for CS Spring 2003Transistor Inverter ExampleIt may be simpler to just think of PMOS and NMOS transistors instead of a general 3 terminal pull-up or pull-down devices or networks.VIN-DPull-Down NetworkVOUTIOUTOutputVDDPull-Up NetworkVIN-UVIN-DVIN-UVOUTIOUTOutputVDDp-type MOSTransistor(PMOS)n-type MOSTransistor(NMOS)Copyright 2001, Regents of University of CaliforniaLecture 20: 04/14/03 A.R. NeureutherVersion Date 04/05/03EECS 42 Intro. electronics for CS Spring 2003VIN= 5Composite IOUTvs. VOUT to Find Points That Satisfies Both Devices for Each VINIOUT(µA)2060100VIN = 3VIN=0 Solution PointsVOUT(V)035VIN=0 & 1IOUT(µA)2060100VIN = 3VIN= 54Copyright 2001, Regents of University of CaliforniaLecture 20: 04/14/03 A.R. NeureutherVersion Date 04/05/03EECS 42 Intro. electronics for CS Spring 2003Voltage Transfer Function for the Complementary Logic CircuitVOUT(V)VIN(V)035350State 1 for VIN= 1VState 3 for VIN= 3VState 5 for VIN = 5VVMVOUT= VINVertical section due to zero slope of IOUTvs. VOUTin the saturation region of both devices.VTUVTDVOUT-SAT-DVOUT-SAT-UPD-OffPU-OffCopyright 2001, Regents of University of CaliforniaLecture 20: 04/14/03 A.R. NeureutherVersion Date 04/05/03EECS 42 Intro. electronics for CS Spring 2003Logic Gate CascadeTo avoid large resistance due to many gates in series, logic functions with 4 or more inputs are usually made from cascading two or more 2-4 input blocks.B2 = VOUT 1The four independent input are A1, B1, A2 and C2.A2 high discharges gate 2 without even waiting for the output of gate 1.C2 high and A2 low makes gate 2 wait for Gate 1 outputA2B2VDDA1B1A1B1VDDVOUT 1B2C2A2C2VOUT 250 fF50 fF5Copyright 2001, Regents of University of CaliforniaLecture 20: 04/14/03 A.R. NeureutherVersion Date 04/05/03EECS 42 Intro. electronics for CS Spring 2003Data Synchronization problem• Combinatorial logic gates can give incorrect answers prematurely and may take several gate propagation delays produce an answer.• Clocks (signals as to when to proceed) and latches (which capture and hold the correct outputs) can provide synchronization.Copyright 2001, Regents of University of CaliforniaLecture 20: 04/14/03 A.R. NeureutherVersion Date 04/05/03EECS 42 Intro. electronics for CS Spring 2003Latch Controlled by a ClockAn inverter with clocked devices in series can form a latch.When the clock φ is high its complement φ is low and the inverter operates.To synchronize the data the clock remains low until the data is correct at all locations on the chip. When the clock goes high the inverse of the data is passed.COUT VDDVOUT φφVIN6Copyright 2001, Regents of University of CaliforniaLecture 20: 04/14/03 A.R. NeureutherVersion Date 04/05/03EECS 42 Intro. electronics for CS Spring 2003Latch Work Best In PairsThe first stage operates while the clock is low and inverts and amplifies the arriving signal and charges or discharges CL1.The second stage operates while the clock is high and inverts the signal on CL1to charge or discharge CL2and downstream logic gate inputs.VDDVOUT VDDVOUT φφφφCL1CL2VINCopyright 2001, Regents of University of CaliforniaLecture 20: 04/14/03 A.R. NeureutherVersion Date 04/05/03EECS 42 Intro. electronics for CS Spring 2003A Double Latch is an Edge-Triggered D Type Flip-FlopVDDVOUT VDDVOUT φφφφCL1CL2VINDuring the low part of the clock cycle this circuit records the input value and when the clock goes high drives VOUT 2 to the voltage level that arrived. (This is the classic function of a D flip-flop.)Note that this circuit is not fooled by noise on the input and makes its decision on the rising edge of the clock (edge-triggered).7Copyright 2001, Regents of University of CaliforniaLecture 20: 04/14/03 A.R. NeureutherVersion Date 04/05/03EECS 42 Intro. electronics for CS Spring 2003Combinatorial Logic and Clocked Latches: WiringA1B1C1A1C1B1VDDVOUT-C1A2B2A2VDDVOUT-C2VDDVOUT-L1VDDVMID-L1 φφφφCL1CL2VIN-L1VDDVOUT-L2VDDVMID-L2 φφφφCL1CL2VIN-L2VDDVOUT-L0VDDVMID-L0 φφφφCL1CL2VIN-L0B2=0Latch 0Latch 2Latch 1Logic 1Logic 2B2A1 =1, C1 =0Copyright 2001, Regents of University of CaliforniaLecture 20: 04/14/03 A.R. NeureutherVersion Date 04/05/03EECS 42 Intro. electronics for CS Spring 2003Combinatorial Logic and Clocked Latches: Signal FlowA1B1C1A1C1B1VDDVOUT-C1A2B2A2VDDVOUT-C2VDDVOUT-L1VDDVMID-L1 φφφφCL1CL2VIN-L1VDDVOUT-L2VDDVMID-L2 φφφφCL1CL2VIN-L2VDDVOUT-L0VDDVMID-L0 φφφφCL1CL2VIN-L0B2=0Latch 0Latch 2Latch 1Logic 1Logic 2B2A1 =0, C1 =0φ HIGH 1φ LOW 1φ HIGH 2φ LOW 2τLOτ2EτLMτ1EτLMτLOτφ−HIGH >
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