Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 10: 10/01/01 A.R. NeureutherVersion Date 11/01/01Midterm Oct. 3, 3:10-4:03 PMClosed Book, Closed Notes, Bring Calculator, Paper ProvidedLast Name A-K 2040 Valley LSB; Last Name L-Z in 10 EvansREMINDEROld Exams Are Posted on WebReview Session 5-6:30 Tu 2060 Valley LSBEE 43 Labs Are Not Cancelled: Students in Tu 6-8PM should go to a different section during 6thweek.Professor Neureuther will not be available Wed. Oct 3rd-Fri Oct. 5thdue to a ConferenceCopyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 10: 10/01/01 A.R. NeureutherVersion Date 11/01/01Lecture 10: October 1, 2001Logic Implementation and SynthesisA)Logic Levels and Gate CircuitsB) Combination of Logic FunctionsC)Synthesis from a Truth TableD)NAND Gate SynthesisE) XOR and Introduction to TimingReading: Schwarz and Oldham 11.2-11.3 pp. 403-422The following slides were derived from those prepared by Professor Oldham For EE 40 in Fall 01Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 10: 10/01/01 A.R. NeureutherVersion Date 11/01/01Logic Gates – How are they used in practice?ABC=A·BANDFirst of all we must agree on what is High (logical 1) or low (logical 0). Suppose 1.5 V is 1 and 0V is logical 0.C would have the value of 1.5 V (logical 1).But it would have the value of 0V logical 0 if either one of the inputs were held at zero V.AND1.5V+-1.5V+-Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 10: 10/01/01 A.R. NeureutherVersion Date 11/01/01Logic Gates – How are they built in practice?(You can learn about building gates in EE 141.)Pull up NetworkVSUPPLYGroundArray of ValvesVINSignalsA,B,CVOUTA Valve is a TransistorValves in Parallel => NORValves in Series => NANDABABCurrent flows when VINis highVINCopyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 10: 10/01/01 A.R. NeureutherVersion Date 11/01/01The most common basic gates are NAND and NOR?ABABAB0001101100011110Not-AND = NANDABABABA+BBA+0001101101111000Not-OR = NORABBA+Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 10: 10/01/01 A.R. NeureutherVersion Date 11/01/01How to Combine Gate to Produce a Desired Logic Function?(More basic Logical Synthesis)ABA•ExampleF= A B.BABA B.Again a little shorthand is usefulCopyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 10: 10/01/01 A.R. NeureutherVersion Date 11/01/01How to Combine Gate to Produce a Desired Logic Function?(More basic Logical Synthesis)Suppose we are given a truth table (all logic statements can be represented by a truth table). How can we implement the function?Answer: There are lots of ways, but one simple way is implementation from “sum of products” formulation.How to do this: 1) Write sum of products expression from truth table and 2) Implement using standard gates.(Warning this is probably inefficient – we need to minimize, or simplify the expression. You will learn this in CS 150.)Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 10: 10/01/01 A.R. NeureutherVersion Date 11/01/01How to Combine Gate to Produce a Desired Logic Function?(More basic Logical Synthesis)Example:01111011010100011010C010010100000FBAorClearly: F= 1 ifC = 1BACAB =1i.e.F= C +ABBACCopyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 10: 10/01/01 A.R. NeureutherVersion Date 11/01/01How to Combine Gate to Produce a Desired Logic Function?(More basic Logical Synthesis)Example:01111011010100011010C010010100000FBAF= C +ABB ACABCABCFCopyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 10: 10/01/01 A.R. NeureutherVersion Date 11/01/01Logical SynthesisGuided by DeMorgan’s TheoremDeMorgan’s Theorem :[] C B A CBA =++or[] C BA CBA =++Example of Using DeMorgan’s Theorem:Thus any sum of products expression can be immediately synthesized from NAND gates aloneCDEAB EDC BA F •=••+•=ABCDFECopyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 10: 10/01/01 A.R. NeureutherVersion Date 11/01/01Logical Synthesis of XOR011101110000FBABABAF•+•=FBAABBAX•=BAY•=Delay 1Delay 2Delay 3We Need a Timing Diagram!Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Lecture 10: 10/01/01 A.R. NeureutherVersion Date 11/01/01Timing Diagram for Delays in LogictimeLogic
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