DOC PREVIEW
Berkeley ELENG 42 - Logic Circuit Supplement

This preview shows page 1-2-3 out of 10 pages.

Save
View full document
View full document
Premium Document
Do you want full access? Go Premium and unlock all 10 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 10 pages.
Access to all documents
Download any document
Ad free experience
View full document
Premium Document
Do you want full access? Go Premium and unlock all 10 pages.
Access to all documents
Download any document
Ad free experience
Premium Document
Do you want full access? Go Premium and unlock all 10 pages.
Access to all documents
Download any document
Ad free experience

Unformatted text preview:

Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Supplement #1: 10/2701 A.R. NeureutherVersion Date 10/27/01Supplement #1: October 27, 2001Logic Circuit SupplementA) Transistor Inverter ExampleB) Terminology and Using VOUT-SAT-DC) States are Voltage Levels of VIND) Single Equation IOUTvs. VOUTE) Composite IOUTvs. VOUT for RPULL-UPF) Composite IOUTvs. VOUT for Active Pull-UpG)Voltage Transfer Function and VMCopyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Supplement #1: 10/2701 A.R. NeureutherVersion Date 10/27/01Transistor Inverter ExampleIt may be simpler to just think of PMOS and NMOS transistorsinstead of a general 3 terminal pull-up or pull-down device.Pull-Down NetworkVOUTIOUTOutputVIN-DVDDPull-Up NetworkVIN-UVOUTIOUTOutputVIN-DVDDVIN-Up-type MOSTransistor(PMOS)n-type MOSTransistor(NMOS)Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Supplement #1: 10/2701 A.R. NeureutherVersion Date 10/27/01TerminologyVDDVINVOUTIOUTOutputRPULL UPVDD= Power supply voltageIOUT= Current into the pull down devicePull-Down(NMOS)Pull-Down Device = Device used to carry current from the output node to ground to discharge the output node to ground.Pull-Up Device = Device used to carry current from the power supply to the output node to charge the output node to the power supply voltage.VTD= Value of VINat which the NMOS transistor begins to conduct.VOUT-SAT-D= Value of VOUTbeyond which the current IOUTno longer increases in the NMOS.Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Supplement #1: 10/2701 A.R. NeureutherVersion Date 10/27/01States are Voltage Levels of VINState 1 or VIN= 1VVOUT(V)03VDD=5IOUT(µA)2060100State 3 or VIN= 3VState 5 or VIN= 5VThe maximum voltage is VDDVOUT-SAT-DCurrent is flat (saturated) beyond VOUT-SAT-DCurrent is zero until VINis larger than VTDCopyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Supplement #1: 10/2701 A.R. NeureutherVersion Date 10/27/01Eliminating Point of ConfusionThe use of VTDtwice in the equation for IOUTis confusing (although it eliminates an extra parameter). Instead we add an extra parameter to distinguish between threshold for conduction which is determined by VINreaching VTDand saturation of the current level when VOUTreaches VOUT-SAT-D.()DSATOUTTDINDPDOUTVVVkI−−−−=()TDTDINDPDOUTVVVkI−=−Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Supplement #1: 10/2701 A.R. NeureutherVersion Date 10/27/01Single Equation EE42 NMOS ModelCurrent IOUTonly flows when VINis larger than the threshold value VTDand the current is proportional to VOUTup to VOUT-SAT-Dwhere it reaches()DSATOUTTDINDPDOUTVVVkI−−−−=VOUT(V)IOUT(µA)0352060100State 3 VIN= 3VLinear (with VOUT)Saturation (with VOUT)Example:kD= 25 µA/V2VTD= 1VVOUT-SAT-D= 1V()AVVVVAIPDOUTµµ50113252=−=−Note that we have added an extra parameter to distinguish between threshold (VTD) and saturation (VOUT-SAT-D).Use these values in the homework.Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Supplement #1: 10/2701 A.R. NeureutherVersion Date 10/27/01Single Equation EE42 PMOS ModelCurrent IOUTonly flows when VINis smaller than VDD minus the threshold value VTUand the current is proportional to (VDD-VOUT) up to (VDD-VOUT-SAT-U) where it reaches()USATOUTTUINDDUPUOUTVVVVkI−−−−−=Example:kU= 20 µA/V2VTU= 1VVOUT-SAT-u= 1V()AVVVVVAIPDOUTµµ201135202=−−=−VOUT(V)IOUT(µA)0352060100State 3 VIN= 3VLinear (with VOUT)Saturation (with VOUT)Use these values in the homework.Copyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Supplement #1: 10/2701 A.R. NeureutherVersion Date 10/27/01Composite IOUTvs. VOUTfor CMOSVOUT(V)03VDD=5IOUT(µA)2060100State 3 or VIN= 3VThe maximum voltage is VDDVOUT-SAT-DPD current is flat (saturated) beyond VOUT-SAT-DPull-Up PMOSPull-Down NMOSPU current is flat (saturated) belowVDD-VOUT-SAT-DSolutionCopyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Supplement #1: 10/2701 A.R. NeureutherVersion Date 10/27/01Voltage Transfer Function for the Complementary Logic CircuitVOUT(V)VIN(V)035350State 1 for VIN= 1VState 3 for VIN= 3VState 5 for VIN = 5VVMVOUT= VINVertical section due to zero slope of IOUTvs. VOUTin the saturation region of both devices.VTUVTDVOUT-SAT-DVOUT-SAT-UCopyright 2001, Regents of University of CaliforniaEECS 42 Intro. electronics for CS Fall 2001 Supplement #1: 10/2701 A.R. NeureutherVersion Date 10/27/01Method for Finding VMAt VM, 1) VOUT= VIN =VM2) Both devices are in saturation3) IOUT-PD= IOUT-PU()()USATOUTTUINDDUPUOUTDSATOUTTDINDPDOUTVVVVkIVVVkI−−−−−−−−==−=)SubstituteVMSolve for VMExample Result: When kD= kP, VOUT-SAT-D= VOUT-SAT-Uand VTD=VTU, then VM=


View Full Document

Berkeley ELENG 42 - Logic Circuit Supplement

Documents in this Course
Lecture 1

Lecture 1

25 pages

Lecture 2

Lecture 2

20 pages

Lecture 3

Lecture 3

21 pages

Midterm 1

Midterm 1

20 pages

Load more
Download Logic Circuit Supplement
Our administrator received your request to download this document. We will send you the file to your email shortly.
Loading Unlocking...
Login

Join to view Logic Circuit Supplement and access 3M+ class-specific study document.

or
We will never post anything without your permission.
Don't have an account?
Sign Up

Join to view Logic Circuit Supplement 2 2 and access 3M+ class-specific study document.

or

By creating an account you agree to our Privacy Policy and Terms Of Use

Already a member?